Serializer/deserializer test modes

• US 7,898,991 B2
• Filed: 10/16/2008
• Issued: 03/01/2011
• Est. Priority Date: 10/16/2008
• Status: Active Grant

• Current Assignee: II-VI Delaware, Inc. (Coherent Corp.)
• Original Assignee: Finisar Corporation (II-VI Incorporated)
• Inventors: Cole, Christopher R.
• Primary Examiner(s): Pham; Chi H
• Assistant Examiner(s): Ng; Fan
• Application Number:
  US12/252,649
• Publication Number:
  US 20100097942A1
• Time in Patent Office: 866 Days
• Field of Search: None
• US Class Current: 370/271
• CPC Class Codes: G06F 11/221 to test buses, lines or interfaces, e.g. stuck-at or open line faults
• CPC Class Codes: H03M 9/00 Parallel/series conversion or vice versa digital stores in which the information is moved stepwise per se G11C19/00
• CPC Class Codes: H04J 14/02 Wavelength-division multiplex systems
• CPC Class Codes: H04J 14/0201 Add-and-drop multiplexing
• CPC Class Codes: H04J 14/028 WDM bus architectures
• CPC Class Codes: H04J 3/047 Distributors with transistors or integrated circuits
• CPC Class Codes: H04J 3/0685 Clock or time synchronisation in a node; Intranode synchronisation
• CPC Class Codes: H04J 3/14 Monitoring arrangements for SDH/SONET rings H04J3/085
• CPC Class Codes: H04L 1/244 test sequence generators

Abstract

Serializer, deserializer, and/or serdes ICs are configured to support one or more test modes to enable end-to-end testing in communication links in which the ICs are implemented. To support the end-to-end testing, the ICs can include a multiplexing stage with means for deterministically mapping a plurality of input parallel data signals to at least one output serial data signal and/or a demultiplexing stage with means for deterministically mapping at least one input serial data signal to a plurality of output parallel data signals. When used in combination in a communication link, the means included in the multiplexing stage and demultiplexing stage deterministically map specific input parallel data signals to specific output parallel data signals.

Claims

1. A multiplexing stage, comprising:

a plurality of input demultiplexers configured to demultiplex a plurality of parallel data signals into a plurality of demultiplexed signals;

a plurality of synchronizing flip flops, each coupled to a different one of the plurality of input demultiplexers and configured to receive and synchronize the plurality of demultiplexed signals into a plurality of retimed signals;

one or more output multiplexers coupled to the synchronizing flip flops and configured to sample the plurality of retimed signals in a pre-defined order to generate one or more serial data signals therefrom; and

means for deterministically mapping the plurality of parallel data signals to the one or more serial data signals, the means for deterministically mapping being coupled between the one or more output multiplexers and at least one of the plurality of synchronizing flip flops, wherein the means for deterministically mapping includes a first plurality of static multiplexers coupled between the one or more output multiplexers and a first synchronizing flip flop, the first plurality of static multiplexers configured to select either a test signal or a first set of the plurality of demultiplexed signals for inclusion in the one or more serial data signals.

2. The multiplexing stage of claim 1, further comprising a pseudo-random bit stream generator configured to generate the test signal.

3. The multiplexing stage of claim 1, wherein the means for deterministically mapping further includes a second plurality of static multiplexers coupled between a first output multiplexer and a second synchronizing flip flop, the second plurality of static multiplexers configured to select either the test signal and part of the first set of the plurality of demultiplexed signals or a second set of the plurality of demultiplexed signals for inclusion in the one or more serial data signals.

4. The multiplexing stage of claim 3, wherein the first set of the plurality of demultiplexed signals corresponds to one parallel data signal included in the plurality of parallel data signals and the second set of the plurality of demultiplexed signals corresponds to another parallel data signal included in the plurality of parallel data signals.

5. A multiplexing stage, comprising:

a plurality of input demultiplexers configured to demultiplex a plurality of parallel data signals into a plurality of demultiplexed signals;

a plurality of synchronizing flip flops, each coupled to a different one of the plurality of input demultiplexers and configured to receive and synchronize the plurality of demultiplexed signals into a plurality of retimed signals;

one or more output multiplexers coupled to the synchronizing flip flops and configured to sample the plurality of retimed signals in a pre-defined order to generate one or more serial data signals therefrom; and

means for deterministically mapping the plurality of parallel data signals to the one or more serial data signals, the means for deterministically mapping being coupled between the one or more output multiplexers and at least one of the plurality of synchronizing flip flops, wherein the multiplexing stage is configured to;

multiplex five parallel data signals, each having a data rate substantially equal to 10 Gigabits per second, into two serial data signals, each having a data rate substantially equal to 25 Gigabits per second;

or

multiplex ten parallel data signals, each having a data rate substantially equal to 10 Gigabits per second, into four serial data signals, each having a data rate substantially equal to 25 Gigabits per second.

6. A demultiplexing stage, comprising:

one or more input demultiplexers configured to demultiplex one or more serial data signals into a plurality of demultiplexed signals;

a plurality of synchronizing flip flops coupled to the one or more input demultiplexers and configured to receive and synchronize the plurality of demultiplexed signals into a plurality of retimed signals;

a plurality of output multiplexers coupled to the plurality of synchronizing flip flops and configured to multiplex the plurality of retimed signals into a plurality of serial data signals; and

means for deterministically mapping the one or more serial data signals to the plurality of serial data signals, the means for deterministically mapping being coupled between the one or more input demultiplexers and at least one of the plurality of synchronizing flip flops.

7. The demultiplexing stage of claim 6 configured to:

demultiplex two serial data signals, each having a data rate substantially equal to 25 Gigabits per second, into five parallel data signals, each having a data rate substantially equal to 10 Gigabits per second;

or

demultiplex four serial data signals, each having a data rate substantially equal to 25 Gigabits per second, into ten parallel data signals, each having a data rate substantially equal to 10 Gigabits per second.

8. The demultiplexing stage of claim 6, wherein the means for deterministically mapping includes a plurality of lock detectors coupled between the one or more input demultiplexers and a first synchronizing flip flop, the plurality of lock detectors configured to search the plurality of demultiplexed signals for a test signal included in the one or more serial data signals.

9. The demultiplexing stage of claim 8, further comprising an interval counter configured to notify the plurality of lock detectors when a time period expires.

10. The demultiplexing stage of claim 9, wherein:

the one or more input demultiplexers demultiplex the one or more serial data signals into the plurality of demultiplexed signals by distributing bits of the one or more serial data signals onto a plurality of signal lanes in a pre-defined order;

the plurality of lock detectors are configured to search for the test signal on specific signal lanes included in the plurality of signal lanes; and

the plurality of lock detectors are further configured to instruct the one or more input demultiplexers to delay by one the distribution of bits of the one or more serial data signals onto the plurality of signal lanes when the plurality of lock detectors do not find the test signal on the specific signal lanes before the time period expires.

11. The demultiplexing stage of claim 8, wherein the means for deterministically mapping further includes a plurality of static multiplexers coupled between a first input demultiplexer, the first synchronizing flip flop, and a first lock detector, the plurality of static multiplexers configured to:

in normal operation, select one of the plurality of demultiplexed signals on a first signal lane to provide to the first synchronizing flip flop;

in a first test mode, select one of the plurality of demultiplexed signals on a second signal lane to provide to one of the plurality of lock detectors; and

in a second test mode, select one of the plurality of demultiplexed signals on a third signal lane to provide to the first synchronizing flip flop and select one of the plurality of demultiplexed signals on a fourth signal lane to provide to the one of the plurality of lock detectors.

12. A method of deterministically mapping a plurality of parallel data signals to at least one serial data signal, comprising:

receiving a plurality of input parallel data signals at a first optoelectronic device;

replacing one of the plurality of input parallel data signals with a first test signal;

multiplexing the first test signal and all but the one of the plurality of input parallel data signals into at least one serial data signal; and

transmitting the plurality of serial data signals to a second optoelectronic device, wherein the second optoelectronic device is configured to;

receive the at least one serial data signal;

demultiplex the at least one serial data signal into a plurality of output parallel data signals; and

attempt to lock on to the test signal while demultiplexing the at least one serial data signal into the plurality of output parallel data signals.

13. The method of claim 12, wherein multiplexing the first test signal and all but the one of the plurality of input parallel data signals into at least one serial data signal includes sampling the bits of the first test signal and all but the one of the plurality of input parallel data signals in a first pre-defined order to generate the at least one serial data signal.

14. The method of claim 13, wherein the second optoelectronic device is configured to demultiplex the at least one serial data signal into a plurality of output parallel data signals by distributing the bits of the at least one serial data signal in a second pre-defined order matching the first pre-defined order.

15. The method of claim 12, wherein the plurality of input parallel data signals includes five parallel data signals, each having a data rate substantially equal to 10 gigabits per second, and the at least one serial data signal includes two serial data signals, each having a data rate substantially equal to 25 gigabits per second.

16. The method of claim 15, wherein each of the two serial data signals is generated from a different two of the five parallel data signals and the test signal, allowing each serial data signal having a data rate substantially equal to 25 gigabits per second to be isolated and tested with 10 gigabit per second test equipment by testing the two corresponding parallel data signals included in the serial data signal.

17. A method of deterministically mapping at least one serial data signal to a plurality of parallel data signals, comprising:

receiving, from a first optoelectronic device, at least one serial data signal at a second optoelectronic device;

demultiplexing the at least one serial data signal into a plurality of demultiplexed data signals that includes a test signal;

searching for the test signal on a specific one of a plurality of signal lanes;

locking onto the test signal when it is found on the specific one of the plurality of signal lanes; and

multiplexing the plurality of demultiplexed data signals into a plurality of serial data signals.

18. The method of claim 17, wherein the at least one serial data signal is demultiplexed into a plurality of demultiplexed data signals by at least one input demultiplexer which distributes the bits of the at least one serial data signal to the plurality of signal lanes in a first pre-defined order.

19. The method of claim 18, wherein the second optoelectronic device searches for the test signal on the specific one of the plurality of signal lanes for a first time period and if the first time period expires without finding the test signal, the input demultiplexers are repeatedly instructed after the first and subsequent time periods to delay by one the distribution of bits of the at least one serial data signal to the plurality of signal lanes.