Method, apparatus and instructions for parallel data conversions
First Claim
Patent Images
1. An apparatus comprising:
- a destination storage location corresponding to a first architectural register;
an execution unit having circuitry to process a packed format values by converting, responsive to a control signal, a first packed first format value in a first format selected from a first plurality of packed first format values in the first format to a first plurality of second format values, said first packed first format value having a plurality of sub elements each having a first number of bits, each of the first plurality of second format values being a number represented in a second format and having a second number of bits which is greater than the first number of bits, said execution unit to store all of said first plurality of second format values into said first architectural register.
1 Assignment
0 Petitions
Accused Products
Abstract
Method, apparatus, and program means for performing a conversion. In one embodiment, a disclosed apparatus includes a destination storage location corresponding to a first architectural register. A functional unit operates responsive to a control signal, to convert a first packed first format value selected from a set of packed first format values into a plurality of second format values. Each of the first format values has a plurality of sub elements having a first number of bits. The second format values have a greater number of bits. The functional unit stores the plurality of second format values into an architectural register.
29 Citations
33 Claims
-
1. An apparatus comprising:
-
a destination storage location corresponding to a first architectural register; an execution unit having circuitry to process a packed format values by converting, responsive to a control signal, a first packed first format value in a first format selected from a first plurality of packed first format values in the first format to a first plurality of second format values, said first packed first format value having a plurality of sub elements each having a first number of bits, each of the first plurality of second format values being a number represented in a second format and having a second number of bits which is greater than the first number of bits, said execution unit to store all of said first plurality of second format values into said first architectural register. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
-
-
15. An apparatus comprising:
-
a decoder to receive a first instruction and to decode said first instruction into a control signal; an execution unit coupled to the decoder the execution unit having circuitry to receive the control signal, the execution unit to responsively process a plurality of floating point values by converting a first plurality of floating point values in a first floating point format having a first number of bits into a first integer value comprising a plurality of sub elements each having a second number of bits less than the first number of bits and to store said first integer value in a first position in a first register, the first register being capable of storing a plurality of integer values in a plurality of individually accessible positions. - View Dependent Claims (16, 17, 18, 19)
-
-
20. A method comprising:
-
a module fetching a first instruction that specifies a location of a first format value in a first format among a plurality of first format values of a packed data, the first format value having a plurality of sub elements each sub element having a first number of bits; an execution unit processing the first format value by converting the first format value to a first plurality of second format values in a second format with circuitry, each of the first plurality of second format values having the second format and corresponding to one of the plurality of sub elements, the second format having a multiple of the first number of bits; storing the first plurality of second format values into a first register. - View Dependent Claims (21, 22, 23, 24, 25)
-
-
26. A system comprising:
-
a memory to store a first instruction and an image processing sequence that operates on image data in a second format; a processor coupled to the memory to process a first operand comprising a plurality of packed integer data values according to the first instruction by converting one of the plurality of packed integer data values into a first plurality of values in a second format and to store said first plurality of values in the second format into a register corresponding to an architectural register, said first plurality of values in the second format being manipulated as part of an image by said image processing sequence; a graphics interface coupled to the processor to receive graphical data representative of the image from said processor; a display to display said image. - View Dependent Claims (27, 28, 29, 30, 31)
-
-
32. A tangible machine readable medium storing an instruction, which if executed by a machine, causes the machine to perform operations of:
-
converting with an arithmetic logic unit an integer value, the integer value being among a plurality of integer values of a packed data and having a first integer format having a plurality of sub elements each having a first number of bits, to a plurality of floating point values, each of the plurality of floating point values having a first floating point format, the first floating point format having a multiple of the first number of bits; storing the plurality of floating point values into a first register, wherein the tangible machine readable medium is one of a memory, a magnetic storage disc, and an optical storage disc. - View Dependent Claims (33)
-
Specification