I/O and memory bus system for DFPs and units with two- or multi-dimensional programmable cell architectures
First Claim
Patent Images
1. A Field Programmable Gate Array (FPGA) Integrated Circuit comprising:
- a cell structure including (a) configurable cells in a two-dimensional array and (b) a configurable internal interconnection that interconnects the configurable cells; and
at least one dedicated hardwired interface unit that;
is separate from the plurality of configurable cells;
is connected to the configurable internal interconnection;
is adapted for transferring processing data between the configurable cells and an external unit at runtime, while the configurable cells are operational;
has at least one state machine controlling said transfer;
includes a protocol generator adapted for generating data transfer protocols; and
has at least one dedicated line transmitting signals to said external unit and at least one dedicated line receiving signals from said external unit.
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Abstract
A general bus system is provided which combines a number of internal lines and leads them as a bundle to the terminals. The bus system control is predefined and does not require any influence by the programmer. Any number of memories, peripherals or other units can be connected to the bus system (for cascading).
548 Citations
42 Claims
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1. A Field Programmable Gate Array (FPGA) Integrated Circuit comprising:
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a cell structure including (a) configurable cells in a two-dimensional array and (b) a configurable internal interconnection that interconnects the configurable cells; and at least one dedicated hardwired interface unit that; is separate from the plurality of configurable cells; is connected to the configurable internal interconnection; is adapted for transferring processing data between the configurable cells and an external unit at runtime, while the configurable cells are operational; has at least one state machine controlling said transfer; includes a protocol generator adapted for generating data transfer protocols; and has at least one dedicated line transmitting signals to said external unit and at least one dedicated line receiving signals from said external unit. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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14. A Field Programmable Gate Array (FPGA) Integrated Circuit comprising:
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a cell structure including (a) configurable cells in a two-dimensional array and (b) a configurable internal interconnection that interconnects the configurable cells; and at least one dedicated hardwired interface unit that; is separate from the plurality of configurable cells; is connected to the configurable internal interconnection; is adapted for transferring processing data between the configurable cells and an external unit at runtime, while the configurable cells are operational; has at least one state machine controlling said transfer; has at least one dedicated line transmitting signals to said external unit and at least one dedicated line receiving signals from said external unit; and combines individual and unrelated lines of the internal interconnection to form a FPGA internal bus. - View Dependent Claims (15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27)
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28. A Field Programmable Gate Array (FPGA) Integrated Circuit comprising:
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a cell structure including (a) configurable cells in a two-dimensional array and (b) a configurable internal interconnection that interconnects the configurable cells; and at least one dedicated hardwired interface unit that; is separate from the plurality of configurable cells; is connected to the configurable internal interconnection; is adapted for transferring processing data between the configurable cells and an external unit at runtime, while the configurable cells are operational; has at least one state machine controlling said transfer; has at least one dedicated line transmitting signals to said external unit and at least one dedicated line receiving signals from said external unit; and defines a FPGA internal bus by a configurable connection of individual and unrelated lines of the internal interconnection to the interface unit. - View Dependent Claims (29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41)
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42. A system comprising:
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a Field Programmable Gate Array (FPGA) Integrated Circuit including a cell structure that includes (a) configurable cells in a two-dimensional array and (b) a configurable internal interconnection that interconnects the configurable cells; and at least one dedicated hardwired interface unit that; is separate from the plurality of configurable cells; is connected to the configurable internal interconnection; is adapted for, at runtime, while the configurable cells are operational, transferring processing data between the configurable cells and an external unit; has at least one state machine controlling said transfer; includes a protocol generator adapted for generating data transfer protocols; and has at least one dedicated line transmitting signals to said external unit and at least one dedicated line receiving signals from said external unit.
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Specification