Uncorrectable error detection utilizing complementary test patterns

• US 7,900,100 B2
• Filed: 02/21/2007
• Issued: 03/01/2011
• Est. Priority Date: 02/21/2007
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Gollub, Marc A.
• Primary Examiner(s): Lamarre; Guy J
• Application Number:
  US11/677,214
• Publication Number:
  US 20080201620A1
• Time in Patent Office: 1,469 Days
• Field of Search: 714/718, 714/719, 714/715, 714/735, 714/785
• US Class Current: 714/718
• CPC Class Codes: G06F 11/1044 with specific ECC/EDC distribution
• CPC Class Codes: G11C 2029/1208 Error catch memory
• CPC Class Codes: G11C 29/42 using error correcting codes [ECC] or parity check
• CPC Class Codes: G11C 29/44 Indication or identification of errors, e.g. for repair
• CPC Class Codes: G11C 29/4401 for self repair

Abstract

A system, method and program product for utilizing error correction code (ECC) logic to detect multi-bit errors. In one embodiment, a first test pattern and a second test pattern are applied to a set of hardware bit positions. The first and second patterns are multiple logic level patterns and the second test pattern is the logical complement of the first test pattern. The first and second test patterns are utilized by the ECC logic to detect correctable errors having n or fewer bits. One or more bit positions of a first correctable error occurring responsive to applying the first test pattern are determined and one or more bit positions of a second correctable error occurring responsive to applying the second test pattern are determined. The determined bit positions of the first and second correctable errors are processed to identify a multiple-bit error within the set of hardware bit positions.

Claims

1. A method for utilizing error correction code (ECC) logic that detects and corrects correctable errors to detect multi-bit errors, said method comprising:

applying a first test pattern and a second test pattern to a set of hardware bit positions, wherein the second test pattern is the logical complement of the first test pattern, wherein the first and second test patterns are utilized by said ECC logic to detect correctable errors having n or fewer bits;

determining one or more bit positions of a first correctable error occurring responsive to applying the first test pattern;

determining one or more bit positions of a second correctable error occurring responsive to applying the second test pattern, wherein one or more of the bit positions of the second correctable error are different than the bit positions of the first correctable error;

processing the determined bit positions of the first and second correctable errors to identify a multiple-bit error within the set of hardware bit positions; and

in response to detecting a multiple-bit error within the set of hardware bit positions resulting from the processing of the determined bit positions of the first and second correctable errors, recording an uncorrectable error record entry, wherein said uncorrectable error record entry includes;

the bit positions of the first and second correctable errors; and

the count and frequency of occurrence of each of the first and second correctable errors.

2. The method of claim 1, wherein said hardware bit positions comprise a memory line having a specified memory address, said applying a first test pattern and a second test pattern to the set of hardware bit positions comprising reading the first test pattern from the memory array bit positions at the specified memory address and subsequently reading the second test pattern from the memory array bit positions at the specified memory address.

3. The method of claim 2, said determining one or more bit positions of the first and second correctable errors comprising:

generating a first correctable error syndrome from the first test pattern read from the memory line; and

generating a second correctable error syndrome from the second test pattern read from the memory line.

4. The method of claim 1, wherein:

the first and second test patterns each include test data bits and parity check bits; and

the method further comprises calculating the parity check bits from the test data bits.

5. The method of claim 1, wherein said first correctable error contains at least one error bit that is the logical complement of at least one error bit in said second correctable error.

6. The method of claim 1, wherein a correctable error is defined by said ECC logic as including n or fewer bits, and wherein said processing the determined bit positions of the first and second correctable errors comprises comparing the bit locations of the first correctable error with the bit locations of the second correctable error to determine whether the first and second correctable errors in combination indicate an m-bit error, wherein m is greater than n.

7. A system for utilizing error correction code (ECC) logic that detects and corrects correctable errors to detect multi-bit errors, said system comprising:

an ECC logic module that applies a first test pattern and a second test pattern to a set of hardware bit positions, wherein the second test pattern is the logical complement of the first test pattern, wherein the first and second test patterns are utilized by said ECC logic to detect correctable errors having n or fewer bits;

an error detection unit that determines one or more bit positions of a first correctable error occurring responsive to applying the first test pattern, said error detection unit determining one or more bit positions of a second correctable error occurring responsive to applying the second test pattern, wherein one or more of the bit positions of the second correctable error are different than the bit positions of the first correctable error;

uncorrectable error storage; and

an uncorrectable error unit that processes the determined bit positions of the first and second correctable errors to identify a multiple-bit error within the set of hardware bit positions and that, responsive to detection of the multiple-bit error within the set of hardware bit positions, records an uncorrectable error record entry in the uncorrectable error storage, wherein said uncorrectable error record entry includes;

the bit positions of the first and second correctable errors; and

the count and frequency of occurrence of each of the first and second correctable errors.

8. The system of claim 7, wherein said hardware bit positions comprise a memory line having a specified memory address, wherein said ECC logic module reads the first test pattern from the memory array bit positions at the specified memory address and subsequently reads the second test pattern from the memory array bit positions at the specified memory address.

9. The system of claim 8, said error detection unit comprising a syndrome generator that generates a first correctable error syndrome from the first test pattern read from the memory line, said syndrome generator generating a second correctable error syndrome from the second test pattern read from the memory line.

10. The system of claim 7, wherein:

the first and second test patterns each include test data bits and parity check bits; and

the system further includes a check bit generator that generates the parity check bits from the test data bits.

11. The system of claim 7, wherein said first correctable error contains at least one error bit that is the logical complement of at least one error bit in said second correctable error.

12. The system of claim 7, wherein a correctable error is defined by said ECC logic as including n or fewer bits, and wherein said uncorrectable error unit compares the bit locations of the first correctable error with the bit locations of the second correctable error to determine whether the first and second correctable errors in combination indicate an m-bit error, wherein m is greater than n.

13. A computer-readable data storage medium having encoded thereon computer-executable instructions for utilizing error correction code (ECC) logic that detects and corrects correctable errors to detect multi-bit errors, said computer-executable instructions adapted to cause a computer to perform:

applying a first test pattern and a second test pattern to a set of hardware bit positions, wherein the second test pattern is the logical complement of the first test pattern, wherein the first and second test patterns are utilized by said ECC logic to detect correctable errors having n or fewer bits;

determining one or more bit positions of a first correctable error occurring responsive to applying the first test pattern;

determining one or more bit positions of a second correctable error occurring responsive to applying the second test pattern, wherein one or more of the bit positions of the second correctable error are different than the bit positions of the first correctable error;

processing the determined bit positions of the first and second correctable errors to identify a multiple-bit error within the set of hardware bit positions; and

in response to detecting a multiple-bit error within the set of hardware bit positions resulting from the processing of the determined bit positions of the first and second correctable errors, recording an uncorrectable error record entry, wherein said uncorrectable error record entry includes;

the bit positions of the first and second correctable errors; and

the count and frequency of occurrence of each of the first and second correctable errors.

14. The computer-readable data storage medium of claim 13, wherein said hardware bit positions comprise a memory line having a specified memory address, said applying a first test pattern and a second test pattern to the set of hardware bit positions comprising reading the first test pattern from the memory array bit positions at the specified memory address and subsequently reading the second test pattern from the memory array bit positions at the specified memory address.

15. The computer-readable data storage medium of claim 14, said determining one or more bit positions of the first and second correctable errors comprising:

generating a first correctable error syndrome from the first test pattern read from the memory line; and

generating a second correctable error syndrome from the second test pattern read from the memory line.

16. The computer-readable data storage medium of claim 13, wherein:

the first and second test patterns each include test data bits and parity check bits; and

the computer-executable instructions cause the computer to calculate the parity check bits from the test data bits.

17. The computer-readable data storage medium of claim 13, wherein said first correctable error contains at least one error bit that is the logical complement of at least one error bit in said second correctable error.

18. The computer-readable data storage medium of claim 13, wherein a correctable error is defined by said ECC logic as including n or fewer bits, and wherein said processing the determined bit positions of the first and second correctable errors comprises comparing the bit locations of the first correctable error with the bit locations of the second correctable error to determine whether the first and second correctable errors in combination indicate an m-bit error, wherein m is greater than n.