Reconstituted wafer level stacking

• US 7,901,989 B2
• Filed: 06/20/2008
• Issued: 03/08/2011
• Est. Priority Date: 10/10/2006
• Status: Active Grant

• Current Assignee: Tessera, Inc. (Adeia Inc.)
• Original Assignee: Tessera, Inc. (Adeia Inc.)
• Inventors: Mohammed, Ilyas, Mirkarimi, Laura Wills, Haba, Belgacem, Ovrutsky, David, Oganesian, Vage
• Primary Examiner(s): Zarneke; David A
• Assistant Examiner(s): Wagner; Jenny L
• Application Number:
  US12/143,743
• Publication Number:
  US 20090160065A1
• Time in Patent Office: 991 Days
• Field of Search: 438/109, 438/110, 438/113, 257/E23.178
• US Class Current: 438/110
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304
• CPC Class Codes: H01L 2221/68377 with parts of the auxiliary support remaining in the finished device
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/24145 the bodies being stacked
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48145 the bodies being stacked
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
• CPC Class Codes: H01L 2224/9202 Forming additional connectors after the connecting process
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/06506 Wire or wire-like electrical connections between devices
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06524 Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 2225/06551 Conductive connections on the side of the device
• CPC Class Codes: H01L 2225/06568 : the devices decreasing in size, e.g. pyramidical stack
• CPC Class Codes: H01L 2225/06582 : Housing for the assembly, e.g. chip scale package [CSP]
• CPC Class Codes: H01L 23/5382 : Adaptable interconnections, e.g. for engineering changes
• CPC Class Codes: H01L 24/24 : of an individual high density interconnect connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/82 : by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 24/96 : the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/207 : Diameter ranges

Abstract

A stacked microelectronic assembly is fabricated from a structure which includes a plurality of first microelectronic elements having front faces bonded to a carrier. Each first microelectronic element may have a first edge and a plurality of first traces extending along the front face towards the first edge. After exposing at least a portion of the first traces, a dielectric layer is formed over the plurality of first microelectronic elements. After thinning the dielectric layer, a plurality of second microelectronic elements are aligned and joined with the structure such that front faces of the second microelectronic elements are facing the rear faces of the plurality of first microelectronic elements. Processing is repeated to form the desirable number of layers of microelectronic elements. In one embodiment, the stacked layers of microelectronic elements may be notched at dicing lines to expose edges of traces, which may then be electrically connected to leads formed in the notches. Individual stacked microelectronic units may be separated from the stacked microelectronic assembly by any suitable dicing, sawing or breaking technique.

Claims

1. A method of fabricating a stacked microelectronic assembly comprising:

a) forming a structure comprising a plurality of first microelectronic elements each having a front face bonded to a carrier and a first edge surface extending away from the front face, and a plurality of first traces extending along said front face towards said first edge surface;

b) removing material from said first edge surfaces to expose at least a portion of each of said first traces;

c) aligning and joining a plurality of second microelectronic elements with said structure such that a front face of each said second microelectronic element is facing a rear face of a first microelectronic element, each second microelectronic element having a second edge surface and a plurality of second traces extending along said front face of said second microelectronic element towards said second edge surface;

d) removing material from said second edge surfaces to expose at least a portion of each of said second traces; and

e) connecting leads to said first and second traces.

2. The method of claim 1 wherein said plurality of first microelectronic elements are spaced apart from one another on said carrier;

and wherein said method further comprises, after step b), forming a dielectric region between said spaced-apart first microelectronic elements of said structure.

3. The method of claim 2 further comprising forming openings in said dielectric region to expose said first and second traces and forming conductive vias in said openings in conductive communication with said first and second traces.

4. The method of claim 1 further comprising thinning said structure comprising said plurality of first microelectronic elements from said rear faces thereof.

8. The method of claim 1 further comprising severing said plurality of joined first and second microelectronic elements into individual units each including first and second aligned microelectronic elements and leads extending from said first and second traces.

9. The method of claim 1 wherein said step (a) further comprises selecting individual ones of said first microelectronic elements from a plurality of unattached first microelectronic elements for bonding to said carrier.

10. The method of claim 1 wherein step c) of aligning and joining said plurality of second microelectronic elements with said structure comprises positioning each of said second microelectronic elements such that said second edge of each second microelectronic element is substantially aligned with said first edge of each said first microelectronic element.

11. The method of claim 1 wherein step c) of aligning and joining said plurality of second microelectronic elements with said structure comprises positioning each of said second microelectronic elements such that said second edge surface of each second microelectronic element is laterally offset from said first edge surface of each said first microelectronic element.

12. The method of claim 1 wherein each of said first and second microelectronic elements comprises a flash memory.

5. A method of fabricating a stacked microelectronic assembly comprising:

a) forming a structure comprising a plurality of first microelectronic elements having front faces bonded to a carrier, each first microelectronic element having a first edge and a plurality of first traces extending along said front face towards said first edge;

b) removing material from said first edges to expose at least a portion of each of said first traces;

c) aligning and joining a plurality of second microelectronic elements with said structure such that a front face of each said second microelectronic element is facing a rear face of a first microelectronic element, each second microelectronic element having a second edge and a plurality of second traces extending along said front face of said second microelectronic element towards said second edge;

d) removing material from said second edges to expose at least a portion of each of said second traces; and

e) connecting leads to said first and second traces,

wherein said step e) further includes forming notches from a top surface of said stacked microelectronic assembly to a depth in said stacked microelectronic assembly sufficient to expose edges of said exposed portions of first and second traces in walls of said notches; and

wherein connecting leads to said first and second traces comprises forming leads in said walls of said notches that electrically contact said exposed edges of said first and second traces.

6. The method of claim 5 wherein forming leads in said walls of said notches further comprises extending said leads from said walls to said top surface of said stacked microelectronic assembly.

7. The method of claim 5 further comprising severing said stacked microelectronic assembly into individual stacked microelectronic units each comprising at least one of each of aligned first and second microelectronic elements;

wherein at least one wall of one of said notches with said leads formed thereon forms a side surface of each individual stacked microelectronic unit.

13. A method of fabricating a stacked microelectronic assembly comprising:

a) forming a first structure comprising a plurality of spaced-apart first microelectronic elements each having a front face bonded to a carrier layer and an opposing rear face;

each first microelectronic element comprising a plurality of first traces extending along said front face towards a first edge of said microelectronic element;

b) from said rear face, removing material from said first edge of each first microelectronic element until at least a portion of each of said first traces is exposed;

c) forming a dielectric layer over said plurality of spaced-apart first microelectronic elements;

said dielectric layer forming a dielectric region between said spaced-apart first microelectronic elements;

d) from said rear faces, thinning said dielectric layer and said plurality of spaced-apart first microelectronic elements to a desired thickness;

e) forming a second structure comprising a plurality of spaced-apart second microelectronic elements by (i) aligning said plurality of spaced-apart second microelectronic elements with said plurality of spaced-apart first microelectronic elements such that a front face of each said second microelectronic element is facing a rear face of a first microelectronic element, and (ii) by joining said plurality of spaced-apart and aligned second microelectronic elements to said first structure;

each second microelectronic element having a second edge and a plurality of second traces extending along said front face of said second microelectronic element towards said second edge;

f) from said rear face, removing material from said second edge of each second microelectronic element until at least a portion of each of said second traces is exposed;

g) forming a dielectric layer over said plurality of spaced-apart second microelectronic elements;

said dielectric layer forming a dielectric region between said spaced-apart second microelectronic elements;

h) from said rear faces, thinning said dielectric layer and said plurality of spaced-apart second microelectronic elements to a desired thickness;

i) forming notches from a top surface of said second structure to a depth in said stacked microelectronic assembly sufficient to expose a cross-sectional edge of each portion of said first and second traces in walls of said notches; and

j) forming leads in said walls of said notches;

said leads electrically connecting said exposed edges of said first and second traces;

said leads extending from said walls to said top surface of said stacked microelectronic assembly.

14. The method of claim 13 wherein said step e) (i) of aligning said plurality of spaced-apart second microelectronic elements with said plurality of spaced-apart first microelectronic elements further comprises aligning said second edge of each said second microelectronic element with said first edge of each said first microelectronic element.

15. The method of claim 13 wherein said step e) (i) of aligning said plurality of spaced-apart second microelectronic elements with said plurality of spaced-apart first microelectronic elements further comprises positioning each second microelectronic element such that said second edge of each second microelectronic element is laterally offset from said first edge of each said first microelectronic element.

16. The method of claim 13 wherein each of said first and second microelectronic elements comprises a flash memory.