CMOS devices with a single work function gate electrode and method of fabrication

• US 7,902,014 B2
• Filed: 01/03/2007
• Issued: 03/08/2011
• Est. Priority Date: 09/28/2005
• Status: Expired due to Fees

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Intel Corporation
• Inventors: Doyle, Brian S., Jin, Been-Yih, Chau, Robert S., Kavalieros, Jack T., Brask, Justin K., Datta, Suman
• Primary Examiner(s): Graybill; David E
• Application Number:
  US11/649,545
• Publication Number:
  US 20070111419A1
• Time in Patent Office: 1,525 Days
• Field of Search: None
• US Class Current: 438/197
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823878 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/068 comprising a junction
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/66439 with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor with an active layer made of a group 13/15 material H01L29/66469
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/775 with one dimensional charge carrier gas channel, e.g. quantum wire FET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

Described herein are a device utilizing a gate electrode material with a single work function for both the pMOS and nMOS transistors where the magnitude of the transistor threshold voltages is modified by semiconductor band engineering and article made thereby. Further described herein are methods of fabricating a device formed of complementary (pMOS and nMOS) transistors having semiconductor channel regions which have been band gap engineered to achieve a low threshold voltage.

Claims

1. A method of forming a pair of pMOS transistors, comprising:

forming a first SiGe channel region on a first pMOS region of a silicon substrate, the first SiGe channel region having a first concentration of Ge;

forming a second SiGe channel region on a second pMOS region of the silicon substrate, the second SiGe channel region having a second concentration of Ge, different than the first concentration of Ge;

forming a gate insulator on the first and second SiGe channel regions;

forming a first gate electrode on the gate insulator over the first SiGe channel region;

forming a second gate electrode on the gate insulator over the second SiGe channel region, wherein the first gate electrode and the second gate electrode have a same mid-gap work function; and

forming a p-type doped source and drain on opposite sides of both the first and second gate electrodes to form a first and second pMOS transistor.

2. The method of claim 1, wherein the first and second SiGe channel regions are substantially free of dopant species.

3. The method of claim 1, wherein forming the first SiGe channel region further comprises forming a first cladding layer comprising the first germanium concentration on a first non-planar silicon body, and wherein forming the second SiGe channel region further comprises forming a second cladding layer comprising the second germanium concentration on a second non-planar silicon body, the first and second non-planar silicon bodies having a pair of opposite sidewalls separated by a distance defining a semiconductor body width.

4. The method of claim 3, wherein forming the first and second cladding layers further comprises:

exposing a first pair of opposite sidewalls of the first non-planar silicon body while masking the second non-planar silicon body;

forming the first cladding layer on the first pair of exposed opposite sidewalls;

exposing a second pair of opposite sidewalls of the second non-planar silicon body and;

forming the second cladding layer on the second pair of opposite sidewalls.

5. The method of claim 3, wherein forming the first and second cladding layer further comprises epitaxially growing a SiGe layer on the first and second non-planar silicon bodies.

6. The method of claim 5, wherein at least one of the first and second cladding layers are grown to the thickness of between 5 Å

and 300 Å and

wherein at least one of the first or second concentration of Ge is between approximately 25% and 30%.

7. The method of claim 1, wherein forming the first gate electrode and the second gate electrode further comprises depositing a titanium nitride layer having a work function between 4.5 and 4.9 on the gate insulator over both the first and second SiGe channel regions.