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CMOS devices with a single work function gate electrode and method of fabrication

  • US 7,902,014 B2
  • Filed: 01/03/2007
  • Issued: 03/08/2011
  • Est. Priority Date: 09/28/2005
  • Status: Expired due to Fees
First Claim
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1. A method of forming a pair of pMOS transistors, comprising:

  • forming a first SiGe channel region on a first pMOS region of a silicon substrate, the first SiGe channel region having a first concentration of Ge;

    forming a second SiGe channel region on a second pMOS region of the silicon substrate, the second SiGe channel region having a second concentration of Ge, different than the first concentration of Ge;

    forming a gate insulator on the first and second SiGe channel regions;

    forming a first gate electrode on the gate insulator over the first SiGe channel region;

    forming a second gate electrode on the gate insulator over the second SiGe channel region, wherein the first gate electrode and the second gate electrode have a same mid-gap work function; and

    forming a p-type doped source and drain on opposite sides of both the first and second gate electrodes to form a first and second pMOS transistor.

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