Fluorine plasma treatment of high-k gate stack for defect passivation

• US 7,902,018 B2
• Filed: 09/26/2007
• Issued: 03/08/2011
• Est. Priority Date: 09/26/2006
• Status: Active Grant

• Current Assignee: Applied Materials Incorporated
• Original Assignee: Applied Materials Incorporated
• Inventors: Kraus, Philip Allan, Ahmed, Khaled Z., Olsen, Christopher
• Primary Examiner(s): PHAM, THANHHA S
• Application Number:
  US11/861,578
• Publication Number:
  US 20080076268A1
• Time in Patent Office: 1,259 Days
• Field of Search: 438/216, 438/591, 438/785, 438/774, 257/E21.625
• US Class Current: 438/216
• CPC Class Codes: H01L 21/28088 the final conductor layer next to the insulator being a composite, e.g. TiN
• CPC Class Codes: H01L 21/28185 with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
• CPC Class Codes: H01L 21/28194 by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition H01L21/28202 takes precedence
• CPC Class Codes: H01L 21/28202 in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
• CPC Class Codes: H01L 21/3115 Doping the insulating layers
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material

Abstract

Embodiments of the present invention generally provide a method for forming a dielectric material with reduced bonding defects on a substrate. In one embodiment, the method comprises forming a dielectric layer having a desired thickness on a surface of a substrate, exposing the substrate to a low energy plasma comprising a fluorine source gas to form a fluorinated dielectric layer on the substrate without etching the dielectric layer, and forming a gate electrode on the substrate. In certain embodiments, the fluorine source gas is a carbon free gas. In certain embodiments, the method further comprises co-flowing a gas selected from the group consisting of argon, helium, N₂, O₂, and combinations thereof with the fluorine source gas.

Claims

1. A method for forming a semiconductor device, comprising:

introducing a substrate into a first processing chamber;

forming a high-k dielectric layer having a desired thickness on a surface of the substrate in the first processing chamber;

transferring the substrate to a second processing chamber without exposing the substrate to ambient;

exposing the substrate to a low energy plasma comprising a fluorine source gas to form a fluorinated high-k dielectric layer on the substrate without etching the high-k dielectric layer in the second processing chamber;

transferring the substrate to a third processing chamber without exposing the substrate to ambient; and

forming a gate electrode on the substrate fluorinated high-k dielectric layer in the third processing chamber.

2. The method of claim 1, wherein the fluorine source gas is selected from a group consisting of F₂, NF₃, HF, and combinations thereof.

3. The method of claim 2, further comprising co-flowing a gas selected from a group consisting of argon, helium, N₂, O₂, and combinations thereof with the fluorine source gas.

4. The method of claim 1, wherein the fluorine source gas comprises a carbon free gas.

5. The method of claim 1, wherein exposing the substrate to a low energy plasma comprising a fluorine source gas occurs at a substrate temperature of less than 100°

C.

6. The method of claim 1, wherein the low energy plasma is formed using a pulsed source inductive plasma.

7. The method of claim 1, wherein the gate electrode is a metal gate electrode selected from a group consisting of titanium, titanium nitride, tantalum, tantalum nitride, tungsten, and tungsten nitride.

8. The method of claim 1, wherein the exposing the substrate to a low energy plasma comprising a fluorine source gas occurs after forming a high-k dielectric layer having a desired thickness on a surface of a substrate.

9. The method of claim 1, wherein a concentration of fluorine in the fluorinated dielectric layer is between 1E14 atoms/cm² and 4E15 atoms/cm².

10. The method of claim 1, wherein the high-k dielectric layer contains at least one material selected from a group consisting of, hafnium oxide, zirconium oxide, hafnium silicate oxides, hafnium aluminate, hafnium lanthanum oxides, lanthanum oxides, and aluminum oxide.

11. The method of claim 1, further comprising:

transferring the substrate to a fourth processing chamber without exposing the substrate to ambient; and

annealing the high-k dielectric layer in the fourth processing chamber prior to transferring the substrate to the second processing chamber.

12. The method of claim 11, further comprising:

transferring the substrate to the fourth processing chamber without exposing the substrate to ambient; and

annealing the fluorinated high-k dielectric layer in the fourth processing chamber prior to transferring the substrate to the third processing chamber.

13. A method of forming a high-k gate stack, comprising:

forming a high-k dielectric layer on a substrate;

annealing the high-k dielectric layer;

exposing the substrate to a low ion energy fluorine containing plasma to form a fluorinated high-k dielectric layer and to passivate oxygen vacancies and other bonding defects in the high-k gate stack;

annealing the fluorinated high-k dielectric layer; and

forming a gate electrode on the fluorinated high-k dielectric layer.

14. The method of claim 13, wherein exposing the substrate to a low ion energy fluorine containing plasma comprises providing an RF power between about 50 watts and about 1000 watts.

15. The method of claim 13, wherein the low ion energy plasma is formed by applying an RF power selected so that no etching of the dielectric layer occurs.

16. The method of claim 13, wherein exposing the substrate to a low ion energy fluorine containing plasma comprises performing a pulse radio frequency plasma process selected from a group consisting of inductive pulse plasma, continuous wave capacitive source plasma, and continuous wave mixed inductive and capacitive source plasma.

17. The method of claim 13, wherein the high-k dielectric layer is a metal oxide containing layer.

18. The method of claim 13, wherein exposing the substrate to a low energy plasma comprising a fluorine source gas occurs at a substrate temperature of less than 100°

C.