Methods of forming field effect transistors, methods of forming field effect transistor gates, methods of forming integrated circuitry comprising a transistor gate array and circuitry peripheral to the gate array, and methods of forming integrated circuitry comprising a transistor gate array including first gates and second grounded isolation gates

• US 7,902,028 B2
• Filed: 03/16/2010
• Issued: 03/08/2011
• Est. Priority Date: 02/02/2006
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Kim, Young Pil, Parekh, Kunal R.
• Primary Examiner(s): MALSAWMA, LALRINFAMKIM HMAR
• Application Number:
  US12/724,589
• Publication Number:
  US 20100173456A1
• Time in Patent Office: 357 Days
• Field of Search: 438/257, 438/270, 257/E21.419
• US Class Current: 438/270
• CPC Class Codes: H01L 21/823456 gate conductors with different shapes, lengths or dimensions
• CPC Class Codes: H01L 21/823462 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/66621 using etching to form a recess at the gate location etching of semiconductor bodies H01L21/302

Abstract

The invention includes methods of forming field effect transistors, methods of forming field effect transistor gates, methods of forming integrated circuitry comprising a transistor gate array and circuitry peripheral to the gate array, and methods of forming integrated circuitry comprising a transistor gate array including first gates and second grounded isolation gates. In one implementation, a method of forming a field effect transistor includes forming masking material over semiconductive material of a substrate. A trench is formed through the masking material and into the semiconductive material. Gate dielectric material is formed within the trench in the semiconductive material. Gate material is deposited within the trench in the masking material and within the trench in the semiconductive material over the gate dielectric material. Source/drain regions are formed. Other aspects and implementations are contemplated.

Claims

1. A method of forming integrated circuitry comprising a transistor gate array and circuitry peripheral to the gate array, comprising:

forming masking material over semiconductive material of a substrate;

forming array circuitry trenches through the masking material and into the semiconductive material;

depositing array gate material within the array circuitry trenches in the masking material and within the array circuitry trenches in the semiconductive material;

after depositing the array gate material, forming peripheral circuitry trenches through the masking material; and

depositing peripheral circuitry gate material within the peripheral circuitry trenches within the masking material.

2. The method of claim 1 wherein forming the peripheral circuitry trenches exposes the semiconductive material of the substrate, and further comprising forming a gate dielectric layer over the exposed semiconductive material of the substrate prior to depositing the peripheral circuitry gate material, the gate dielectric layer also forming over the array gate material.

3. The method of claim 2 wherein the gate dielectric layer is formed on the array gate material.

4. The method of claim 3 wherein forming at least a majority of the gate dielectric layer comprises thermal oxidation of the exposed semiconductive material and of the array gate material.

5. The method of claim 1 wherein the array circuitry trenches are formed using a masking step, and further comprising forming grounded gate trenches through the masking material in the array in the same masking step in which the array circuitry trenches are formed.

6. The method of claim 1 wherein the peripheral circuitry trenches are formed using a masking step, and further comprising forming grounded gate trenches through the masking material in the array in the same masking step in which the peripheral circuitry trenches are formed.

7. The method of claim 1 wherein the masking material comprises silicon dioxide received over silicon nitride.

8. The method of claim 1 wherein the depositing of the array gate material at least fills the array circuitry trenches in the masking material and the array circuitry trenches in the semiconductive material with the array gate material.

9. The method of claim 1 wherein the depositing of the array gate material overfills the array circuitry trenches in the masking material and the array circuitry trenches in the semiconductive material with the array gate material.

10. The method of claim 1 wherein the depositing of the peripheral circuitry gate material at least fills the peripheral circuitry trenches in the masking material and the peripheral circuitry trenches in the semiconductive material with the peripheral circuitry gate material.

11. The method of claim 1 wherein the depositing of the peripheral circuitry gate material overfills the peripheral circuitry trenches in the masking material and the peripheral circuitry trenches in the semiconductive material with the peripheral circuitry gate material.

12. The method of claim 1 comprising removing at least a majority of the masking material after depositing the peripheral circuitry gate material.

13. The method of claim 1 being void of photolithographic patterning of the array gate material after its deposition.

14. The method of claim 1 being void of photolithographic patterning of the peripheral circuitry gate material after its deposition.

15. The method of claim 1 being void of photolithographic patterning of the array gate material after its deposition, and being void of photolithographic patterning of the peripheral circuitry gate material after its deposition.

16. The method of claim 1 comprising forming some peripheral circuitry trenches and some array circuitry trenches in the same masking step.

17. A method of forming integrated circuitry comprising a transistor gate array and circuitry peripheral to the gate array, comprising:

forming masking material over semiconductive material of a substrate;

forming array circuitry trenches through the masking material and into the semiconductive material;

depositing array gate material within the array circuitry trenches in the masking material and within the array circuitry trenches in the semiconductive material;

forming peripheral circuitry trenches through the array gate material and through the masking material; and

depositing peripheral circuitry gate material within the peripheral circuitry trenches within the array gate material and within the masking material.

18. A method of forming field effect transistor gates, comprising:

forming masking material over semiconductive material of a substrate, the substrate comprising a trench isolation region;

in a common masking step, forming a first trench through the masking material and into the semiconductive material and forming a second grounded isolation gate trench through the masking material over the trench isolation region; and

in a common deposition step, depositing gate material within the first trench and second trench.

19. The method of claim 18 comprising forming the second grounded isolation gate trench to within the trench isolation region during the common masking step.

20. The method of claim 18 wherein the depositing of the gate material at least fills the first and second trenches with the gate material.

21. The method of claim 18 wherein the depositing of the gate material overfills the first and second trenches with the gate material.

22. The method of claim 18 wherein the masking material comprises silicon dioxide received over silicon nitride.

23. The method of claim 18 comprising removing at least a majority of the masking material after depositing the gate material.

24. The method of claim 18 being void of photolithographic patterning of the gate material after its deposition.

25. The method of claim 18 wherein depositing the gate material covers the masking material with gate material, and comprising removing the gate material selectively relative to and exposing the masking material effective to isolate the gate material within the first and second trenches.

26. The method of claim 18 wherein the masking step comprises photolithography.

27. A method of forming integrated circuitry comprising a transistor gate array including first gates and second grounded isolation gates, comprising:

forming masking material over semiconductive material of a substrate, the substrate comprising trench isolation regions;

forming first trenches through the masking material and into the semiconductive material for the first gates;

forming second grounded isolation gate trenches through the masking material to within the trench isolation regions for the second grounded isolation gates; and

depositing gate material within the first and second trenches.

28. The method of claim 27 comprising forming the first and second trenches at the same time.

29. The method of claim 27 comprising forming the second trenches after forming the first trenches.

30. The method of claim 27 comprising forming the second trenches to within the trench isolation regions.

31. The method of claim 30 comprising forming the first and second trenches at the same time.

32. The method of claim 30 comprising forming the second trenches after forming the first trenches.

33. The method of claim 27 wherein the depositing of gate material within the first and second trenches occurs in the same deposition step.

34. The method of claim 27 wherein the depositing of gate material within the first and second trenches occurs in different deposition steps.

35. The method of claim 27 wherein some of the depositing of gate material within the first and second trenches occurs in the same deposition step, and another some of the depositing of gate material within the first and second trenches occurs in different deposition steps.

36. The method of claim 27 wherein the depositing of the gate material at least fills the first and second trenches with the gate material.

37. The method of claim 27 wherein the depositing of the gate material overfills the first and second trenches with the gate material.

38. The method of claim 27 wherein the masking material comprises silicon dioxide received over silicon nitride.

39. The method of claim 27 comprising removing at least a majority of the masking material after depositing the gate material.

40. The method of claim 27 being void of photolithographic patterning of the gate material after its deposition.

41. The method of claim 27 wherein depositing the gate material covers the masking material with gate material, and comprising removing the gate material selectively relative to and exposing the masking material effective to isolate the gate material within the first and second trenches.

42. A method of forming integrated circuitry comprising a transistor gate array and circuitry peripheral to the gate array, comprising:

forming masking material over semiconductive material of a substrate, the substrate comprising a trench isolation region;

in a common masking step, forming array circuitry trenches through the masking material and into the semiconductive material and forming a grounded isolation gate trench through the masking material into the trench isolation region;

in a common deposition step, depositing array gate material within the array circuitry trenches in the masking material, within the array circuitry trenches in the semiconductive material, and within the grounded isolation gate trench within the trench isolate region;

after depositing the array gate material, forming peripheral circuitry trenches through the masking material; and

depositing peripheral circuitry gate material within the peripheral circuitry trenches within the masking material.