Post passivation interconnection schemes on top of the IC chips
First Claim
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1. A method for fabricating a chip, comprising:
- providing a silicon substrate, a first interconnecting structure over said silicon substrate, wherein said first interconnecting structure comprises multiple sub-micron lines formed by a sub-micron process comprising a damascene process, an electroplating process and a CMP process, multiple patterned circuit layers over said silicon substrate, and multiple dielectric layers between said multiple patterned circuit layers; and
forming a polymer layer and a second interconnecting structure over said silicon substrate, wherein said second interconnecting structure is in said polymer layer, wherein said forming said second interconnecting structure comprises a tens-micron process comprising forming a first metal layer, next forming a patterned photoresist layer, next electroplating a second metal layer, next removing said patterned photoresist layer, and then etching said first metal layer.
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Abstract
A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric, a thick second layer of dielectric is created over the surface of the layer of passivation. Thick and wide interconnect lines are created in the thick second layer of dielectric. The first layer of dielectric may also be eliminated, creating the wide thick interconnect network on the surface of the layer of passivation that has been deposited over the surface of a substrate.
157 Citations
20 Claims
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1. A method for fabricating a chip, comprising:
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providing a silicon substrate, a first interconnecting structure over said silicon substrate, wherein said first interconnecting structure comprises multiple sub-micron lines formed by a sub-micron process comprising a damascene process, an electroplating process and a CMP process, multiple patterned circuit layers over said silicon substrate, and multiple dielectric layers between said multiple patterned circuit layers; and forming a polymer layer and a second interconnecting structure over said silicon substrate, wherein said second interconnecting structure is in said polymer layer, wherein said forming said second interconnecting structure comprises a tens-micron process comprising forming a first metal layer, next forming a patterned photoresist layer, next electroplating a second metal layer, next removing said patterned photoresist layer, and then etching said first metal layer. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A method for fabricating a circuit component, comprising:
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providing a silicon substrate, a first interconnecting structure over said silicon substrate, wherein said first interconnecting structure comprises multiple sub-micron lines formed by a sub-micron process comprising a damascene process, an electroplating process and a CMP process, multiple patterned circuit layers over said silicon substrate, multiple dielectric layers between said multiple patterned circuit layers, and a passivation layer over said first interconnecting structure, over said multiple patterned circuit layers and over said multiple dielectric layers, wherein said passivation layer comprises a nitride; and forming a polymer layer and a second interconnecting structure over said passivation layer, wherein said second interconnecting structure is in said polymer layer, wherein said forming said second interconnecting structure comprises a tens-micron process comprising forming a first metal layer, next forming a patterned photoresist layer, next electroplating a second metal layer, next removing said patterned photoresist layer, and then etching said first metal layer. - View Dependent Claims (9, 10, 11, 12, 13, 14)
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15. A method for fabricating a chip, comprising:
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providing a silicon substrate, a dielectric layer over said silicon substrate, a first interconnecting structure over said silicon substrate and in said dielectric layer, a second interconnecting structure over said silicon substrate and in said dielectric layer, wherein said first and second interconnecting structures are formed by a process comprising a damascene process, an electroplating process and a CMP process, and a separating layer over said dielectric layer, wherein said separating layer comprises a nitride; and forming a ground interconnect and a polymer layer over said separating layer, wherein said polymer layer has a portion over said ground interconnect, wherein said first interconnecting structure is connected to said second interconnecting structure through said ground interconnect, wherein said forming said ground interconnect comprises forming a first metal layer, next forming a patterned photoresist layer, next electroplating a second metal layer, next removing said patterned photoresist layer, and then etching said first metal layer. - View Dependent Claims (16, 17)
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18. A method for fabricating a chip, comprising:
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providing a silicon substrate, a dielectric layer over said silicon substrate, a first interconnecting structure over said silicon substrate and in said dielectric layer, a second interconnecting structure over said silicon substrate and in said dielectric layer, wherein said first and second interconnecting structures are formed by a process comprising a damascene process, an electroplating process and a CMP process, and a separating layer over said dielectric layer, wherein said separating layer comprises a nitride; and forming a signal interconnect and a polymer layer over said separating layer, wherein said polymer layer has a portion over said signal interconnect, wherein said first interconnecting structure is connected to said second interconnecting structure through said signal interconnect, wherein said forming said signal interconnect comprises forming a first metal layer, next forming a patterned photoresist layer, next electroplating a second metal layer, next removing said patterned photoresist layer, and then etching said first metal layer. - View Dependent Claims (19, 20)
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Specification