Method for forming active and gate runner trenches

• US 7,902,071 B2
• Filed: 07/06/2010
• Issued: 03/08/2011
• Est. Priority Date: 01/05/2006
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Marchant, Bruce Douglas
• Primary Examiner(s): Pham; Thanh V
• Application Number:
  US12/830,770
• Publication Number:
  US 20100311216A1
• Time in Patent Office: 245 Days
• Field of Search: 438/39, 438/42, 438/259, 438/270, 438/671, 438/717, 438/736, 438/942, 438/950, 257/E21.023
• US Class Current: 438/671
• CPC Class Codes: H01L 21/3083 characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: Y10S 438/942 Masking
• CPC Class Codes: Y10S 438/95 Multilayer mask including nonradiation sensitive layer

Abstract

A method for forming a trench-gated field effect transistor (FET) includes the following steps. Using a first mask, defining and simultaneously forming a plurality of active gate trenches and at least one gate runner trench extending to a first depth within a silicon region such that (i) the at least one gate runner trench has a width greater than a width of each of the plurality of active gate trenches, and (ii) the plurality of active gate trenches are contiguous with the at least one gate runner trench; and using the first mask and a second mask for protecting the at least one gate runner trench, further extending only the plurality of active gate trenches to a second and final depth within the silicon region.

Claims

1. A method of forming a trench-gated field effect transistor (FET), comprising:

using a first mask, defining and simultaneously forming a plurality of active gate trenches and at least one gate runner trench extending to a first depth within a silicon region such that (i) the at least one gate runner trench has a width greater than a width of each of the plurality of active gate trenches, and (ii) the plurality of active gate trenches are contiguous with the at least one gate runner trench; and

using the first mask and a second mask for protecting the at least one gate runner trench, further extending only the plurality of active gate trenches to a second and final depth within the silicon region.

2. The method of claim 1 further comprising:

forming a recessed layer inside the plurality of active gate trenches and inside the at least one gate runner trench using CMP.

3. The method of claim 2 wherein the recessed layer is a thick bottom dielectric (TBD) formed along a bottom portion of the plurality of active gate trenches and the gate runner trench.

4. The method of claim 2 wherein the recessed layer is a polysilicon layer forming a gate electrode in each of the plurality of active gate trenches and a gate runner in the gate runner trench, wherein the gate electrode and the gate runner are contiguous.

5. The method of claim 1 further comprising:

forming a recessed gate electrode in each of the plurality of active gate trenches and a recessed gate runner in the at least one gate runner trench; and

forming a dielectric cap over the gate electrode in each of the plurality of active gate trenches and over the gate runner in the gate runner trench using CMP.

6. The method of claim 1 wherein the plurality of active gate trenches extend perpendicularly to the at least one gate runner trench.

7. The method of claim 1 wherein the first mask is used to form at least one termination trench in a termination region of the silicon region simultaneously with the plurality of active gate trenches and the at least one gate runner trench.

8. The method of claim 1 further comprising:

forming a thick bottom dielectric (TBD) along a bottom portion of the plurality of active gate trenches and the at least one gate runner trench using CMP.

9. The method of claim 8 further comprising:

forming a recessed gate electrode inside each of the plurality of active gate trenches and a recessed gate runner inside the at least one gate runner trench using CMP.

10. The method of claim 9 further comprising:

forming a dielectric cap over the gate electrode in each of the plurality of active gate trenches and over the gate runner in the gate runner trench using CMP.

11. The method of claim 10 further comprising:

forming a contact opening in the dielectric cap over the recessed gate runner; and

forming an interconnect layer contacting the gate runner through the contact opening.

12. The method of claim 10 wherein the silicon region has a first conductivity type, the method further comprising:

forming a well region of a second conductivity type in the silicon region;

forming source regions of the first conductivity type in the well region; and

forming a first metal layer electrically contacting the well region and the source regions, and a second metal layer contacting the recessed gate runner.