Two-sided surround access transistor for a 4.5F2 DRAM cell

• US 7,902,598 B2
• Filed: 06/24/2005
• Issued: 03/08/2011
• Est. Priority Date: 06/24/2005
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Juengling, Werner
• Primary Examiner(s): Warren; Matthew E
• Application Number:
  US11/166,721
• Publication Number:
  US 20060289919A1
• Time in Patent Office: 2,083 Days
• Field of Search: 257/301, 257329-331, 257/520, 257/E29.257, 257/E29.26
• US Class Current: 257/331
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383
• CPC Class Codes: H10B 12/34 the transistor being at least partially in a trench in the substrate

Abstract

An isolation transistor having a grounded gate is formed between a first access transistor construction and a second access transistor construction to provide isolation between the access transistor constructions of a memory device. In an embodiment, the access transistor constructions are recess access transistors. In an embodiment, the memory device is a DRAM. In another embodiment, the memory device is a 4.5F2 DRAM cell.

Claims

1. A memory device comprising;

a semiconductor substrate;

a plurality of charge storage devices coupled with the semiconductor substrate;

a plurality of digit lines coupled with the semiconductor substrate;

a plurality of gates each electrically interposed between a charge storage device and a digit line wherein a gate, a charge storage device and a digit line define a memory cell, wherein each of the gates is formed so as to be recessed into the semiconductor substrate such that a first depletion region is formed within the semiconductor substrate and such that, when the gate is activated, a conductive path is formed about the perimeter of the recessed gate within the semiconductor substrate to thereby allow charge to flow between the charge storage device and the corresponding digit line;

a plurality of isolation structures each formed so as to be recessed within the semiconductor substrate so as to isolate adjacent memory cells and so as to define a second depletion region for each of the isolation structures within the semiconductor substrate, wherein the plurality of isolation structures are biased such that the second depletion region merges with the corresponding first depletion region to isolate adjacent cells from each other.

2. The device of claim 1, wherein the plurality of isolation structures are biased so as to define the second depletion region.

3. The device of claim 2, wherein the plurality of isolation structures are grounded.

4. The device of claim 2, wherein the plurality of isolation structures are biased such that the second depletion region merges with the corresponding first depletion region such that the doping level of the semiconductor substrate can be reduced without increasing the leakage current between memory cells.

5. The device of claim 1, wherein each of the plurality of cells comprise a first and a second plurality of recessed gates and a first and a second charge storage device and wherein each of the plurality of cells include a common source/drain region that is common between the first and second gates and is electrically coupled to a single digit line.

6. The device of claim 5, further comprising a plurality of source/drain regions that are electrically coupled to the charge storage device.

7. The device of claim 1, wherein the substrate comprises a p-doped substrate and wherein the plurality of recessed gates comprise recessed access devices.

8. The device of claim 1, further comprising a word line that is used to activate the gate of a plurality of cells and wherein the bit line also electrically connects to a plurality of cells and wherein the gate of each cell defines an active area and wherein the active area of each cell is oriented at an angle of 45 degrees with respect to the bit line and word line.

9. The device of claim 1, further comprising a word line that is used to activate the gate of a plurality of cells and wherein the bit line also electrically connects to a plurality of cells and wherein the gate of each cell defines an active area and wherein the active area of each cell is oriented at an angle of 0 degrees with respect to the bit line.

10. The memory device of claim 1 wherein the isolation structure is biased so as not to electrically conduct.

11. The memory device of claim 10 wherein the isolation structure is biased such that the isolation structure is in the depletion mode.

12. The memory device of claim 10 wherein the isolation structure is biased such that the isolation structure is in the accumulation mode.

13. The memory device of claim 1 wherein the isolation structure comprises a grounded recessed gate.