Semiconductor device and method for manufacturing same

• US 7,902,610 B2
• Filed: 02/25/2010
• Issued: 03/08/2011
• Est. Priority Date: 10/16/2006
• Status: Active Grant

• Current Assignee: Sony Corporation (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: Tai, Kaori, Tsukamoto, Masanori, Nakata, Masashi, Oshiyama, Itaru
• Primary Examiner(s): DANG, TRUNG Q
• Application Number:
  US12/712,809
• Publication Number:
  US 20100148274A1
• Time in Patent Office: 376 Days
• Field of Search: 257/369, 257/E21.632, 257/E27.062, 438/233
• US Class Current: 257/369
• CPC Class Codes: H01L 21/76895 Local interconnects; Local pads, as exemplified by patent document EP0896365
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 21/823871 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate

Abstract

A semiconductor device including an N-channel insulated gate field effect transistor and a P-channel insulated gate field effect transistor, the device having: a first insulating layer and a second insulating layer; and gate electrode contact plugs. Each of the gate electrodes of the N-channel insulated gate field effect transistor and the P-channel insulated gate field effect transistor is buried in a gate electrode formation opening provided in the first insulating layer.

Claims

1. A semiconductor device including an N-channel insulated gate field effect transistor, a P-channel insulated gate field effect transistor and an insulating layer, wherein:

each gate electrode of the N-channel insulated gate field effect transistor and the P-channel insulated gate field effect transistor is buried in a gate electrode formation opening provided in the insulating layer,

the gate electrode of the N-channel insulated gate field effect transistor is composed of a first conductive material,

the gate electrode of the P-channel insulated gate field effect transistor is composed of a second conductive material different from the first conductive material, and

interconnect layers respectively cover a whole top surface of a respective one of the gate electrodes of the N-channel insulated gate field effect transistor and the P-channel insulated gate field effect transistor.

2. The semiconductor device according to claim 1, wherein

the interconnect layer covering the top surface of the gate electrode of the N-channel insulated gate field effect transistor and the interconnect layer covering the top surface of the gate electrode of the P-channel insulated gate field effect transistor comprise a common interconnect layer.

3. The semiconductor device according to claim 1, wherein

the insulating layer exists between the gate electrode of the N-channel insulated gate field effect transistor and the gate electrode of the P-channel insulated gate field effect transistor.

4. The semiconductor device according to claim 1, wherein

the interconnect layers are each composed of one conductive material layer.

5. The semiconductor device according to claim 1, wherein

the interconnect layers each have a multilayer structure formed of a lower conductive material layer and an upper conductive material layer, and

the lower conductive material layer is formed of a silicon layer and the upper conductive material layer is formed of a silicide layer.

6. A method for manufacturing a semiconductor device including an N-channel insulated gate field effect transistor and a P-channel insulated gate field effect transistor, the method comprising the steps of:

preparing a base that includes (a) channel forming regions and source/drain regions of the N-channel insulated gate field effect transistor and the P-channel insulated gate field effect transistor, (b) an insulating layer, (c) gate electrode formation openings in the insulating layer for the N-channel insulated gate field effect transistor and the P-channel insulated gate field effect transistor, and (d) a gate insulating film at least on bottoms of the gate electrode formation openings;

forming a gate electrode composed of a first conductive material in the gate electrode formation opening for the N-channel insulated gate field effect transistor, and

forming a gate electrode composed of a second conductive material different from the first conductive material in the gate electrode formation opening for the P-channel insulated gate field effect transistor; and

forming interconnect layers that each cover a whole top surface of a respective one of the gate electrodes of the N-channel insulated gate field effect transistor and the P-channel insulated gate field effect transistor.

7. The method for manufacturing a semiconductor device according to claim 6, wherein the step of forming interconnect layers includes the steps of:

forming an upper insulating layer on an entire surface;

selectively removing partial portions of the upper insulating layer above the top surfaces of the gate electrodes of the N-channel insulated gate field effect transistor and the P-channel insulated gate field effect transistor, to thereby provide interconnect layer trenches in the upper insulating layer;

filling the interconnect layer trenches with a conductive material layer; and

removing the conductive material layer on the upper insulating layer.

8. The method for manufacturing a semiconductor device according to claim 6, wherein the step of forming interconnect layers includes the steps of:

forming a silicon layer;

patterning the silicon layer;

forming a metal layer on an entire surface;

carrying out heat treatment for a reaction between a metal of the metal layer and silicon of the silicon layer to thereby form the interconnect layers each formed of a metal silicide layer; and

removing the metal layer on the insulating layer.