Semiconductor die with through-hole via on saw streets and through-hole via in active area of die

• US 7,902,638 B2
• Filed: 09/25/2007
• Issued: 03/08/2011
• Est. Priority Date: 05/04/2007
• Status: Active Grant

• Current Assignee: JCET Semiconductor (Shaoxing) Co., Ltd.
• Original Assignee: Stats Chippac Limited
• Inventors: Chua, Linda Pei Ee, Do, Byung Tai, Kuan, Heap Hoe
• Primary Examiner(s): Tran; Minh-Loan T
• Assistant Examiner(s): YEUNG LOPEZ, FEIFEI
• Application Number:
  US11/861,251
• Publication Number:
  US 20080272465A1
• Time in Patent Office: 1,260 Days
• Field of Search: None
• US Class Current: 257/620
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/18 High density interconnect [HDI] connectors; Manufacturing methods related thereto
• CPC Class Codes: H01L 2224/2101 Structure
• CPC Class Codes: H01L 2224/215 Material
• CPC Class Codes: H01L 2224/221 Disposition
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48145 the bodies being stacked
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48472 the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
• CPC Class Codes: H01L 2224/73204 : the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73265 : Layer and wire connectors
• CPC Class Codes: H01L 2224/73267 : Layer and HDI connectors
• CPC Class Codes: H01L 2224/81801 : Soldering or alloying
• CPC Class Codes: H01L 2224/82039 : using a laser
• CPC Class Codes: H01L 2225/06506 : Wire or wire-like electrical connections between devices
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06527 : Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 2225/06541 : Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 23/3128 : the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/481 : Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 24/19 : Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 24/82 : by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 25/03 : all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/18162 : of a chip with build-up interconnect
• CPC Class Codes: H01L 2924/19107 : off-chip wires
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/30105 : Capacitance

Abstract

A semiconductor wafer contains a plurality of die with contact pads disposed on a first surface of each die. Metal vias are formed in trenches in the saw street guides and are surrounded by organic material. Traces connect the contact pads and metal vias. The metal vias can be half-circle vias or full-circle vias. Metal vias are also formed through the contact pads on the active area of the die. Redistribution layers (RDL) are formed on a second surface of the die opposite the first surface. Repassivation layers are formed between the RDL for electrical isolation. The die are stackable and can be placed in a semiconductor package with other die. The vias through the saw streets and vias through the active area of the die, as well as the RDL, provide electrical interconnect to the adjacent die.

Claims

1. A semiconductor wafer, comprising:

a plurality of die with contact pads disposed on a first surface of an active area of each die, the semiconductor wafer having saw street guides between each die;

a plurality of first metal vias formed in the saw street guides and surrounded by organic material;

a plurality of second metal vias formed in the active area of the die; and

a plurality of traces connecting the contact pads and first metal vias.

2. The semiconductor wafer of claim 1, further including:

a plurality of redistribution layers (RDL) formed on a second surface of the die opposite the first surface; and

a plurality of repassivation layers formed between the RDL on the second surface of the die.

3. The semiconductor wafer of claim 1, wherein the die are stackable and connected by the first and second metal vias when stacked.

4. The semiconductor wafer of claim 1, wherein at least one metal via is formed between the contact pads on adjacent die.

5. The semiconductor wafer of claim 4, wherein the semiconductor wafer is singulated through the at least one metal via to form metal vias electrically connected to the contact pads by the traces.

6. The semiconductor wafer of claim 1, wherein two metal vias are formed side by side between the contact pads on adjacent die.

7. The semiconductor wafer of claim 6, wherein the semiconductor wafer is singulated along the saw street guides between the two metal vias to form metal vias electrically connected to the contact pads by the traces.

8. The semiconductor wafer of claim 1, further including solder bumps electrically connected to the RDL.

9. A semiconductor package, comprising:

a plurality of stacked die, each die including,

(a) a plurality of contact pads disposed on a first surface of an active area of the die,

(b) a plurality of first metal vias formed along a perimeter of the die,

(c) a plurality of second metal vias formed in the active area of the die, and

(d) a plurality of traces electrically connecting the first metal vias to the contact pads;

a plurality of redistribution layers (RDL) formed on a second surface of the die opposite the first surface; and

a plurality of repassivation layers formed between the RDL on the second surface of the die;

wherein the first and second metal vias provide electrical interconnect between the stacked die.

10. The semiconductor package of claim 9, wherein the semiconductor wafer is singulated through the at least one metal via to form metal vias electrically connected to the contact pads by the traces.

11. The semiconductor package of claim 9, wherein two metal vias are formed side by side between the contact pads on adjacent die.

12. The semiconductor package of claim 11, wherein the semiconductor wafer is singulated along saw street guides between the two metal vias to form metal vias electrically connected to the contact pads by the traces.

13. A semiconductor package, comprising:

a first semiconductor die having contact pads and a plurality of first metal vias formed along a perimeter of the die electrically connected to the contact pads through a plurality of traces, the first semiconductor die further including a plurality of second metal vias formed through an active area of the die;

a second semiconductor die disposed adjacent to the first semiconductor die and electrically connected to the first semiconductor die through the first and second metal vias; and

bond wires electrically connecting the first and second semiconductor die.

14. The semiconductor package of claim 13, wherein two metal vias are formed side by side.

15. The semiconductor package of claim 14, wherein the semiconductor wafer is singulated along saw street guides between the two metal vias to form metal vias electrically connected to the contact pads by the traces.