Microfeature workpieces having interconnects and conductive backplanes, and associated systems and methods

• US 7,902,643 B2
• Filed: 08/31/2006
• Issued: 03/08/2011
• Est. Priority Date: 08/31/2006
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Tuttle, Mark E.
• Primary Examiner(s): Fahmy; Wael M
• Assistant Examiner(s): Kalam; Abul
• Application Number:
  US11/514,568
• Publication Number:
  US 20080054444A1
• Time in Patent Office: 1,650 Days
• Field of Search: 257/659
• US Class Current: 257/659
• CPC Class Codes: H01L 21/76895 Local interconnects; Local pads, as exemplified by patent document EP0896365
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/05001 Internal layers
• CPC Class Codes: H01L 2224/05009 Bonding area integrally formed with a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05155 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05181 Tantalum [Ta] as principal constituent
• CPC Class Codes: H01L 2224/05184 Tungsten [W] as principal constituent
• CPC Class Codes: H01L 2224/0557 the external layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/13 of an individual bump connector
• CPC Class Codes: H01L 2224/13025 the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06527 Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 23/552 Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 24/03 Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/10 : Bump connectors bumps on insulating substrates, e.g. chip carriers, H01L23/49816; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01018 : Argon [Ar]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15787 : Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding

Abstract

Microfeature workpieces having interconnects and conductive backplanes and associated systems and methods are disclosed herein. One such device includes a semiconductor substrate having integrated circuitry and terminals electrically coupled to the integrated circuitry. The device also includes electrically conductive interconnects extending through at least a portion of the semiconductor substrate and electrically coupled to corresponding terminals. The device further includes a conductive backplane assembly having a conductive layer at a back side of the semiconductor substrate. One or more of the interconnects are electrically coupled to the conductive layer at the back side of the semiconductor substrate.

Claims

1. A microelectronic device, comprising:

a semiconductor substrate including integrated circuitry and terminals electrically coupled to the integrated circuitry;

electrically conductive interconnects extending through at least a portion of the semiconductor substrate and electrically coupled to corresponding terminals; and

a conductive backplane assembly comprising

a conductive layer at a back side of the semiconductor substrate, wherein the conductive layer includes an array of openings aligned with corresponding interconnects such that back side post portions of the interconnects extend through at least a portion of the respective openings in the conductive layer; and

dielectric spacers in the openings between the conductive layer and the back side post portions of the corresponding interconnects, wherein at least one interconnect is electrically coupled to the conductive layer, and wherein at least one other interconnect is electrically isolated from the conductive layer.

2. The microelectronic device of claim 1 wherein the electrically conductive interconnects comprise a first interconnect and a second interconnect, and wherein the microelectronic device further comprises:

a first conductive coupler attached to the first interconnect and in electrical contact with the conductive layer at the back side of the semiconductor substrate; and

a second conductive coupler attached to the second interconnect, wherein the second conductive coupler is electrically isolated from the conductive layer.

3. The microelectronic device of claim 1 wherein:

the electrically conductive interconnects comprise a first interconnect and a second interconnect; and

the conductive backplane assembly further comprises

a first dielectric layer on the back side of the substrate and in contact with the first and second interconnects;

the conductive layer over at least a portion of the first dielectric layer and having openings around the first and second interconnects, wherein portions of the first dielectric layer are in the openings between the conductive layer and the first and second interconnects; and

a second dielectric layer over the first dielectric layer and the conductive layer, the second dielectric layer including a first opening over the first interconnect and a second opening over the second interconnect, wherein the first opening is sized to expose a back side portion of the first interconnect, a portion of the first dielectric layer adjacent to the first interconnect, and a portion of the conductive layer adjacent to the first interconnect, and wherein the second opening is sized to expose a back side portion of the second interconnect without exposing the conductive layer adjacent to the second interconnect; and

the device further comprises (a) a first conductive coupler in the first opening and in contact with the first interconnect and the exposed portion of the conductive layer adjacent to the first interconnect, and (b) a second conductive coupler in the second opening and in contact with the second interconnect, wherein the second conductive coupler is electrically isolated from the conductive layer.

4. The microelectronic device of claim 3 wherein:

the first dielectric layer comprises a low temperature CVD oxide;

the conductive layer comprises Al, Cu, Ni, W, and/or a conductive polymer; and

the second dielectric layer comprises a low temperature CVD oxide and/or a photosensitive polyimide.

5. The microelectronic device of claim 1 wherein:

the electrically conductive interconnects comprise a first interconnect and a second interconnect;

the conductive layer on the back side of the substrate has openings around the first and second interconnects, and wherein the conductive backplane assembly further comprises

a dielectric layer over the conductive layer, the dielectric layer including a first opening over the first interconnect and a second opening over the second interconnect, wherein the first opening is sized to expose a back side portion of the first interconnect and a portion of the conductive layer adjacent to the first interconnect, and wherein the second opening is sized to expose a back side portion of the second interconnect without exposing the conductive layer; and

the device further comprises (a) a first conductive coupler in the first opening and in contact with the first interconnect and the exposed portion of the conductive layer adjacent to the first interconnect, and (b) a second conductive coupler in the second opening and in contact with the second interconnect, wherein the second conductive coupler is electrically isolated from the conductive layer.

6. The microelectronic device of claim 5 wherein:

the conductive layer comprises an argon pre-sputter, at least one of a titanium layer and a tantalum layer, and an aluminum layer; and

the dielectric layer comprises a low temperature CVD oxide and/or a photosensitive polyimide.

7. The microelectronic device of claim 1 wherein:

the electrically conductive interconnects comprise a first interconnect and a second interconnect; and

the conductive layer on the back side of the substrate has a first opening around the first interconnect and the conductive layer directly contacts an end of the second interconnect, and wherein the conductive backplane assembly further comprises

a dielectric layer over the conductive layer, the dielectric layer including a first opening over the first interconnect to expose a back side portion of the first interconnect, and a second opening aligned with the second interconnect to expose the conductive layer over a back side portion of the second interconnect; and

the device further comprises (a) a first conductive coupler in the first opening and in contact with the first interconnect, wherein the first conductive coupler is electrically isolated from the conductive layer, and (b) a second conductive coupler in the second opening and in direct contact with the conductive layer.

8. The microelectronic device of claim 7 wherein:

the conductive layer comprises Al, Cu, Ni, W, and/or a conductive polymer; and

the dielectric layer comprises a low temperature CVD oxide and/or a photosensitive polyimide.

9. A microelectronic device, comprising:

a semiconductor substrate including a front side, a back side opposite the front side, integrated circuitry, and an array of bond-pads at the front side electrically coupled to the integrated circuitry;

a plurality of electrically conductive interconnects extending through the substrate, the interconnects having first portions electrically coupled with corresponding bond-pads and second portions at the back side;

a metal layer at the back side of the semiconductor substrate having an array of openings aligned with corresponding interconnects, wherein the second portion of at least one of the interconnects is received in a corresponding opening;

a dielectric layer over the metal layer, the dielectric layer having openings aligned with the interconnects; and

a plurality of solder balls attached to corresponding interconnects at the back side of the semiconductor substrate, wherein at least one of the solder balls is configured to electrically couple the integrated circuitry to the metal layer within the footprint of the semiconductor substrate and at least one solder ball is electrically isolated from the metal layer.

10. The microelectronic device of claim 9 wherein the metal layer comprises at least one of Al, Cu, Ni, and W deposited over a layer of at least one of titanium and tantalum.

11. The microelectronic device of claim 9 wherein the plurality of electrically conductive interconnects comprises a first interconnect and a second interconnect and the dielectric layer comprises a second dielectric layer, and wherein

the microelectronic device further comprises a first dielectric layer on the back side of the substrate and in contact with the first and second interconnects, wherein the first dielectric layer isolates the metal layer from direct contact with the substrate and the first and second interconnects;

the second dielectric layer includes a first opening having a first cross-sectional dimension over the first interconnect and a second opening having a second cross-sectional dimension less than the first cross-sectional dimension over the second interconnect, wherein the first opening is sized to expose the second portion of the first interconnect and a portion of the metal layer adjacent to the first interconnect, and wherein the second opening is sized to expose only the second portion of the second interconnect, and

the plurality of solder balls attached to corresponding interconnects at the back side of the semiconductor substrate comprises (a) a first solder ball in the first opening and in contact with the first interconnect and the adjacent portion of the metal layer, and (b) a second solder ball in the second opening and in contact with the second interconnect, wherein the second solder ball is electrically isolated from the metal layer.

12. The microelectronic device of claim 9 wherein the plurality of electrically conductive interconnects comprises a first interconnect and a second interconnect, and wherein:

the dielectric layer includes a first opening having a first cross-sectional dimension over the first interconnect and a second opening having a second cross-sectional dimension less than the first cross-sectional dimension over the second interconnect, wherein the first opening is sized to expose the second portion of the first interconnect and a portion of the metal layer adjacent to the first interconnect, and wherein the second opening is sized to expose only the second portion of the second interconnect, and

the plurality of solder balls attached to corresponding interconnects at the back side of the semiconductor substrate comprises (a) a first solder ball in the first opening and in contact with the first interconnect and the adjacent portion of the metal layer, and (b) a second solder ball in the second opening and in contact with the second interconnect, wherein the second solder ball is electrically isolated from the metal layer.

13. A microelectronic device, comprising:

a semiconductor substrate including integrated circuitry and bond-pads electrically coupled to the integrated circuitry;

electrically conductive through-substrate interconnects in contact with corresponding bond-pads and having back side portions; and

an EMI shield at a back side of the semiconductor substrate for EMI shielding, the EMI shield comprising

a conductive layer having apertures aligned with corresponding interconnects, wherein the back side portions of the interconnects extend through at least a portion of the corresponding apertures;

a dielectric layer over the metal layer, the dielectric layer having openings aligned with the interconnects; and

a plurality of conductive couplers attached to corresponding interconnects at the back side of the semiconductor substrate, wherein the back side portion of at least one interconnect is electrically coupled to the EMI shield with one of the conductive couplers, and wherein the back side portion of at least one other interconnect and corresponding conductive coupler is electrically isolated from the EMI shield.

14. The microelectronic device of claim 13 wherein the interconnects are positioned to electrically couple the integrated circuitry to the EMI shield within the footprint of the semiconductor substrate.

15. A microelectronic assembly, comprising:

a first microelectronic device having

a first microelectronic die with a first integrated circuit and an array of first bond-pads electrically coupled to the first integrated circuit;

first electrically conductive interconnects extending at least partially through the first die and in contact with corresponding first bond-pads; and

a first conductive backplane assembly comprising

a first conductive layer at a back side of the first die, wherein the first conductive layer includes an array of first openings aligned with corresponding first interconnects such that back side post portions of the first interconnects are accessible through the first openings in the first conductive layer; and

first dielectric spacers in the first openings between the first conductive layer and the back side post portions of the corresponding first interconnects, wherein at least one first interconnect is electrically coupled to the first conductive layer and at least one other first interconnect is electrically isolated from the first conductive layer; and

a second microelectronic device coupled to the first microelectronic device in a stacked configuration, the second microelectronic device having

a second microelectronic die with a second integrated circuit and an array of second bond-pads electrically coupled to the second integrated circuit;

second electrically conductive interconnects extending at least partially through the second die and in contact with corresponding second bond-pads; and

a second conductive backplane assembly comprising

a second conductive layer at a back side of the second die, wherein the second conductive layer includes an array of second openings aligned with corresponding second interconnects such that back side post portions of the second interconnects are accessible through the firs second t openings in the second conductive layer; and

second dielectric spacers in the second openings between the second conductive layer and the back side post portions of the corresponding second interconnects, wherein at least one second interconnect is electrically coupled to the second conductive layer and at least one other second interconnect is electrically isolated from the second conductive layer.

16. The microelectronic assembly of claim 15 wherein the first device is a memory device and the second device is an imager.

17. The microelectronic assembly of claim 15 wherein the first device is a processor and the second device is an imager.

18. The microelectronic assembly of claim 15 wherein the first device is a NAND flash memory and the second device is a random access memory device.

19. The microelectronic assembly of claim 15 wherein the first device and the second device are memory devices.

20. A microelectronic device, comprising:

a semiconductor substrate including a front side, a back side opposite the front side, integrated circuitry, and an array of bond-pads at the front side of the substrate electrically coupled to the integrated circuitry;

a plurality of electrically conductive interconnects extending through the substrate, the interconnects having front side portions electrically coupled with corresponding bond-pads, and back side post portions at the back side of the substrate;

a conductive layer at the back side of the substrate having an array of openings aligned with corresponding interconnects such that the back side post portions of the interconnects extend through the openings in the conductive layer; and

dielectric spacers in the openings between the conductive layer and the back side post portions of the corresponding interconnects, wherein the back side post portions of first interconnects are electrically coupled to the conductive layer, and the back side post portions of second interconnects are electrically isolated from the conductive layer.

21. The microelectronic device of claim 20, further comprising:

a dielectric cover layer over the conductive layer and the back side post portions of the first and second interconnects, the cover layer including first openings over the first interconnects and second openings over the second interconnects, wherein the first openings are sized to expose the back side post portions of the first interconnects and a portion of the conductive layer adjacent to the first interconnects, and wherein the second openings are sized to expose only the back side post portions of the interconnects;

first conductive couplers in the first openings and in contact with the back side post portions of the first interconnects and the exposed portions of the conductive layer proximate to the corresponding first interconnects; and

second conductive couplers in the second openings and in contact with the back side post portions of the second interconnects, wherein the second conductive couplers are electrically isolated from the conductive layer.

22. A microfeature workpiece including a semiconductor substrate having a front side and a back side, the workpiece comprising:

a plurality of microelectronic dies on and/or in the semiconductor substrate, the individual dies including integrated circuitry, an array of bond-pads electrically coupled to the integrated circuitry, a plurality of electrically conductive through-substrate interconnects electrically coupled to corresponding bond-pads, a back side metal layer having an array of openings aligned with corresponding interconnects such that back side post portions of the interconnects extend through at least a portion of the respective openings, and dielectric spacers in the openings between the back side metal layer and the back side post portions of the corresponding interconnects, wherein at least one of the interconnects is electrically coupled to the metal layer, and wherein at least one other interconnect is electrically isolated from the metal layer; and

a plurality of scribe lines spacing apart the individual dies.