Structure and manufacturing method of a chip scale package with low fabrication cost, fine pitch and high reliability solder bump

• US 7,902,679 B2
• Filed: 10/31/2007
• Issued: 03/08/2011
• Est. Priority Date: 03/05/2001
• Status: Expired due to Term

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Megica Corporation (Chipbond Technology Corporation)
• Inventors: Lei, Ming-Ta, Lin, Mou-Shiung, Lin, Chuen-Jye
• Primary Examiner(s): Zarneke; David A
• Application Number:
  US11/981,138
• Publication Number:
  US 20080067677A1
• Time in Patent Office: 1,224 Days
• Field of Search: 257/778
• US Class Current: 257/778
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/05572 the external layer extending out of an opening
• CPC Class Codes: H01L 2224/06136 Covering only the central area of the surface to be connected, i.e. central arrangements
• CPC Class Codes: H01L 2224/13007 Bump connector smaller than the underlying bonding area, e.g. than the under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/13017 being non uniform along the bump connector
• CPC Class Codes: H01L 2224/13023 the whole bump connector protruding from the surface
• CPC Class Codes: H01L 2224/1308 being stacked
• CPC Class Codes: H01L 2224/13083 Three-layer arrangements
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13155 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 24/06 of a plurality of bonding areas
• CPC Class Codes: H01L 24/12 Structure, shape, material or disposition of the bump connectors prior to the connecting process
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 24/17 of a plurality of bump connectors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00013 : Fully indexed content
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01018 : Argon [Ar]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01042 : Molybdenum [Mo]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/12044 : OLED
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/351 : Thermal stress

Abstract

A new method and package is provided for the mounting of semiconductor devices that have been provided with small-pitch Input/Output interconnect bumps. Fine pitch solder bumps, consisting of pillar metal and a solder bump, are applied directly to the I/O pads of the semiconductor device, the device is then flip-chip bonded to a substrate. Dummy bumps may be provided for cases where the I/O pads of the device are arranged such that additional mechanical support for the device is required.

Claims

1. A chip package comprising:

a substrate;

a semiconductor device comprising a polymer layer and a metal pad having a contact point aligned with an opening in said polymer layer;

a copper pillar between said contact point and said substrate, wherein said copper pillar has a height between 10 and 100 micrometers, wherein said copper pillar is connected to said contact point through said opening;

a titanium-containing layer between said contact point and said copper pillar, wherein said titanium-containing layer is on said contact point, on said polymer layer and in said opening, wherein said copper pillar is connected to said contact point through said titanium-containing layer;

a solder between said copper pillar and said substrate, wherein said solder joins said substrate, wherein said solder is connected to said copper pillar; and

an underfill between said semiconductor device and said substrate, wherein said underfill contacts said semiconductor device and said substrate and covers a sidewall of said copper pillar.

2. The chip package of claim 1 further comprising a nickel-containing layer between said solder and said copper pillar.

3. The chip package of claim 2, wherein said nickel-containing layer has a thickness between 1 and 10 micrometers.

4. The chip package of claim 2, wherein said sidewall of said copper pillar is recessed from a sidewall of said nickel-containing layer.

5. The chip package of claim 1, wherein said titanium-containing layer comprises titanium nitride.

6. A chip package comprising:

a substrate;

a semiconductor device comprising a polymer layer and a metal pad having a contact point aligned with an opening in said polymer layer;

a copper pillar between said contact point and said substrate, wherein said copper pillar has a height between 10 and 100 micrometers, wherein said copper pillar is connected to said contact point through said opening;

a solder between said copper pillar and said substrate, wherein said solder joins said substrate, wherein said solder is connected to said copper pillar; and

an underfill between said semiconductor device and said substrate, wherein said underfill contacts said semiconductor device and said substrate and covers a sidewall of said copper pillar.

7. The chip package of claim 6 further comprising a nickel-containing layer between said solder and said copper pillar.

8. The chip package of claim 7, wherein said nickel-containing layer has a thickness between 1 and 10 micrometers.

9. The chip package of claim 7, wherein said sidewall of said copper pillar is recessed from a sidewall of said nickel-containing layer.

10. The chip package of claim 6 further comprising a metal layer between said contact point and said copper pillar, wherein said metal layer is on said contact point, on said polymer layer and in said opening, wherein said copper pillar is connected to said contact point through said metal layer.

11. A chip package comprising:

a substrate;

a semiconductor device comprising a polymer layer and a metal pad having a contact point aligned with an opening in said polymer layer;

a solder between said contact point and said substrate, wherein said solder joins said substrate, wherein said solder is connected to said contact point through said opening;

a titanium-containing layer between said contact point and said solder, wherein said titanium-containing layer is on said contact point, on said polymer layer and in said opening;

a copper-containing layer between said solder and said titanium-containing layer, wherein said solder is connected to said copper-containing layer, wherein said copper-containing layer has a first sidewall recessed from a second sidewall of said titanium-containing layer; and

an underfill between said semiconductor device and said substrate, wherein said underfill contacts said semiconductor device and said substrate and covers a surface of said solder.

12. The chip package of claim 11, wherein said copper-containing layer has a thickness between 10 and 100 micrometers.

13. The chip package of claim 11 further comprising a nickel-containing layer between said copper-containing layer and said solder.

14. The chip package of claim 13, wherein said nickel-containing layer has a thickness between 1 and 10 micrometers.

15. The chip package of claim 11, wherein said titanium-containing layer comprises a titanium-tungsten alloy.

16. A chip package comprising:

a substrate;

a semiconductor device comprising a polymer layer and a metal pad having a contact point aligned with an opening in said polymer layer;

a solder between said contact point and said substrate, wherein said solder joins said substrate, wherein said solder is connected to said contact point through said opening;

a first metal layer between said contact point and said solder, wherein said first metal layer is on said contact point, on said polymer layer and in said opening;

a second metal layer between said solder and said first metal layer, wherein said solder is connected to said second metal layer, wherein said second metal layer has a first sidewall recessed from a second sidewall of said first metal layer; and

an underfill between said semiconductor device and said substrate, wherein said underfill contacts said semiconductor device and said substrate and covers a surface of said solder.

17. The chip package of claim 16, wherein said first metal layer comprises tungsten.

18. The chip package of claim 16, wherein said second metal layer comprises a copper layer between said first metal layer and said solder.

19. The chip package of claim 16 further comprising a nickel-containing layer between said second metal layer and said solder.

20. The chip package of claim 16, wherein said first metal layer comprises titanium.