Low dropout regulator with stability compensation circuit

• US 7,902,801 B2
• Filed: 08/04/2009
• Issued: 03/08/2011
• Est. Priority Date: 12/30/2005
• Status: Expired due to Fees

• Current Assignee: ST-Ericcson SA (Telefonaktiebolaget LM Ericsson)
• Original Assignee: ST-Ericcson SA (Telefonaktiebolaget LM Ericsson)
• Inventors: Mandal, Sajal Kumar
• Primary Examiner(s): Behm; Harry
• Application Number:
  US12/535,433
• Publication Number:
  US 20090289610A1
• Time in Patent Office: 581 Days
• Field of Search: 323/273, 323/270, 323/280, 323274-279, 323/281
• US Class Current: 323/273
• CPC Class Codes: G05F 1/575 characterised by the feedback circuit

Abstract

The present invention provides a low dropout (LDO) regulator with a stability compensation circuit. A “zero frequency” tracking as well as “non-dominant parasitic poles'"'"' frequency reshaping” are performed to achieve a good phase margin for the LDO by means of the compensation circuit. In this compensation method neither a large load capacitor nor its equivalent series resistance is needed to stabilize a regulator. LDO regulators, in system on chip application, having load capacitors in the range of few nano-Farads to few hundreds of nano-Farads can be efficiently compensated with this compensation method. A dominant pole for the regulator is realized at an internal node and the second pole at an output node of the regulator is tracked with a variable capacitor generated zero over a range of load current to cancel the effect of each other. A third pole of the system is pushed out above the unity gain frequency of the open loop transfer function with the help of the frequency compensation circuit. The compensation technique is very effective in realizing a low power, low-load-capacitor LDO desirable for system on chip applications.

Claims

1. A stability compensation circuit for a low dropout regulator, the low dropout regulator including a driver transistor, the circuit comprising:

a first compensation transistor having a gate coupled to a gate of the driver transistor, a source coupled to an unregulated input voltage, and a drain;

a compensation capacitor coupled between the gate and the drain of the compensation transistor;

a second compensation transistor having a gate coupled to a drain of the driver transistor, a drain coupled to the unregulated input voltage, and a source;

a resistor coupled between the drain of the first compensation transistor and the source of the second compensation transistor; and

a source of bias current coupled to the source of the second compensation transistor,

wherein the compensation capacitor remains in an accumulation region at no load current to provide a maximum capacitance, and the capacitance of said compensation capacitor decreases with a load current during a higher load current region.

2. The stability compensation circuit of claim 1 wherein the ratio of the size of the driver transistor to the size of the first compensation transistor is K to 1.

3. The stability compensation circuit of claim 1 wherein the driver transistor comprises a P-channel driver transistor.

4. The stability compensation circuit of claim 1 wherein the first compensation transistor comprises a P-channel compensation transistor.

5. The stability compensation circuit of claim 1 wherein the second compensation transistor comprises an N-channel compensation transistor.

6. The stability compensation circuit of claim 1 wherein the source of bias current comprises an N-channel transistor.

7. The stability compensation circuit of claim 1 wherein the low dropout regulator further comprises an error amplifier responsive to a difference between a predetermined reference voltage and a function of a regulated output voltage to produce an error signal.

8. The stability compensation circuit of claim 1 further comprising a load capacitor coupled to an output terminal of the low dropout regulator.

9. The stability compensation circuit of claim 8 wherein a typical value of the load capacitor is about 100 nF.

10. The stability compensation circuit of claim 1 wherein a typical value of the resistor is about 43 K ohms.

11. The stability compensation circuit of claim 1 wherein a typical value of the compensation capacitor is about 128 pF.

12. The stability compensation circuit of claim 1 wherein the second compensation transistor comprises a source follower transistor.

13. The stability compensation circuit of claim 1 wherein the compensation capacitor comprises a voltage dependent compensation capacitor.

14. The stability compensation circuit of claim 1 wherein the first compensation transistor comprises a parasitic pole reshaping P-channel transistor operating in a saturation region.

15. The stability compensation circuit of claim 8 wherein the load capacitor is in the range of a few nano-Farads to a few hundred nano-Farads.

16. The stability compensation circuit of claim 1 comprising a first pole for the regulator realized at an internal node.

17. The stability compensation circuit of claim 16 further comprising a second pole at an output node of the regulator that is tracked with a variable compensation capacitor generated zero over a range of load current.

18. The stability compensation circuit of claim 17 further comprising a third pole that is pushed out above a unity gain frequency of an open loop transfer function.

19. A stability compensation circuit for a low dropout regulator, the low dropout regulator including a driver transistor, the circuit comprising:

a first compensation transistor having a gate coupled to a gate of the driver transistor, a source coupled to an unregulated input voltage, and a drain;

a compensation capacitor coupled between the gate and the drain of the compensation transistor;

a second compensation transistor having a gate coupled to a drain of the driver transistor, a drain coupled to the unregulated input voltage, and a source;

a resistor coupled between the drain of the first compensation transistor and the source of the second compensation transistor;

a source of bias current coupled to the source of the second compensation transistor;

a first pole for the regulator realized at an internal node; and

a second pole at an output node of the regulator that is tracked with a variable compensation capacitor generated zero over a range of load current.

20. The stability compensation circuit of claim 19 further comprising a third pole that is pushed out above a unity gain frequency of an open loop transfer function.