Apparatus and method for test structure inspection

• US 7,902,849 B2
• Filed: 01/03/2007
• Issued: 03/08/2011
• Est. Priority Date: 01/03/2006
• Status: Active Grant

• Current Assignee: Applied Materials Israel Limited (Applied Materials Incorporated)
• Original Assignee: Applied Materials Israel Limited (Applied Materials Incorporated)
• Inventors: Bullock, Eugene T.
• Primary Examiner(s): Nguyen; Ha Tran T
• Assistant Examiner(s): ISLA RODAS, RICHARD
• Application Number:
  US11/619,496
• Publication Number:
  US 20070267632A1
• Time in Patent Office: 1,525 Days
• Field of Search: 324754-765, 324/751
• US Class Current: 324/754.22
• CPC Class Codes: G01R 31/2884 using dedicated test connectors, test elements or test circuits on the IC under test G01R31/2855 takes precedence
• CPC Class Codes: G01R 31/305 using electron beams investigating or analysing materials by measuring photoelectric effect G01N23/227
• CPC Class Codes: H01L 22/14 for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means

Abstract

Herein are described layouts of test structures and scanning methodologies that allow large probe currents to be used so as to allow the detection of resistive defects with a resistance lower than 1 MΩ while at the same time allowing a sufficient degree of localization to be obtained for root cause failure analysis. The detection of resistances lower than 1 MΩ nominally requires a probe current greater than 1 micro ampere for detection on an electron beam inspection system.

Claims

1. A method, comprising:

scanning a plurality of test structures on a wafer using a high current microscope of an electron beam inspection system, the high current microscope having a probe beam current greater than 1 μ

A, each of the plurality of test structures having a pad end and an end opposite the pad end, the first test structure being longer in one dimension than in a second dimension, and further having a conducting pad electrically connected to the structure at the pad end thereof, the conducting pad having a larger contiguous area than that of the first test structure and being sized sufficiently to allow the entire current of the probe beam to enter the first test structure and saturate a capacitance of the first test structure to the wafer;

monitoring detected signals from the wafer during the scanning to detect electrical errors present in a first test structure of the plurality of test structures;

upon detecting an electrical error, storing a position of the first test structure;

operating a stage to bring the first test structure under a scan field of a second electron microscope of the electron beam inspection system; and

localizing the electrical error using the second electron microscope.

2. The method of claim 1 wherein the pad end of the first test structure is electrically floating, and the end opposite the pad end of the first test structure is electrically coupled to the wafer.

3. The method of claim 1, wherein the pad end and the end opposite the pad end of the first test structure are electrically floating, and the end opposite the pad end of the first test structure is electrically coupled to a capacitor.

4. The method of claim 1, wherein the first test structure is a contact or via chain system.

5. The method of claim 1, wherein the first test structure is formed in a double serpentine pattern.

6. The method of claim 1 wherein the first test structure is positioned in relation to a second test structure so as to allow testing of both the first and second test structures.

7. The method of claim 6, wherein the first and second test structures form a comb structure for testing shorts between adjacent metal lines.

8. The method of claim 1, wherein the first test structure is arranged sequentially along a direction of an axis of the stage so as to enable sequential scanning of the test structures.

9. The method of claim 1, wherein the first test structure is arranged sequentially in a mirror format along a direction of an axis of the stage so as to enable sequential scanning of the test structures.

10. The method of claim 1, wherein the electrical error comprises a resistive defect within a portion of the first test structure.