Repairable IO in an integrated circuit

• US 7,902,855 B1
• Filed: 03/03/2010
• Issued: 03/08/2011
• Est. Priority Date: 03/03/2010
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Lewis, David
• Primary Examiner(s): Le; Don P
• Application Number:
  US12/717,022
• Time in Patent Office: 370 Days
• Field of Search: 326/9, 326/10, 326 37- 41
• US Class Current: 326/10
• CPC Class Codes: H03K 19/17744 for input/output signals
• CPC Class Codes: H03K 19/17764 for reliability

Abstract

Methods and structures for implementing repairable input/output (IO) circuitry in an integrated circuit (IC) arc disclosed. One embodiment of the present invention includes repairable IO circuitry along a right, left, or inner column of an IC. Another embodiment includes repairable IO circuitry along a top, bottom, or inner row of an IC. In one embodiment, normal and redundant mode routing is provided between IO buffer circuits and IO register circuits. In another embodiment, normal and redundant mode routing is also provided between IO register circuits and routing to core regions of the IC. One embodiment provides normal and redundant mode routing between two or more IO registers that may span more than one row and/or more than one IO block. One embodiment provides normal and redundant mode routing for different types of IO registers. In some embodiments, redundant mode IO connections shift along with redundant mode connections in a core logic region of the IC. In other embodiments, redundant mode IO connections operate to repair IO circuitry independently of any redundancy scheme in the IC'"'"'s core regions.

Claims

1. An integrated circuit comprising:

a plurality of input/output (IO) buffer circuits;

a plurality of IO register circuits including spare IO register circuits; and

a plurality of selection circuits, a selection circuit of the plurality of selection circuits being coupled to normal mode routing between a first IO buffer circuit and a first IO register circuit and to redundant mode routing between the first IO buffer circuit and a second IO register circuit such that if an IO register circuit is not usable, a spare IO register circuit may be utilized and at least certain selection circuits can be configured to select redundant mode routing rather than normal mode routing.

2. The integrated circuit of claim 1 wherein the IO buffer circuits, the IO register circuits, and the selection circuits are arranged along a left, right, or inner column of the integrated circuit and an IO register circuit of the plurality of IO register circuits is coupled to horizontal routing to a core region of the integrated circuit.

3. The integrated circuit of claim 1 wherein at least some of the IO register circuits are coupled to other IO register circuits of the plurality of IO register circuits, the integrated circuit further comprising a second plurality of selection circuits, a selection circuit of the second plurality of selection circuits being coupled to normal mode routing between a first and second IO register circuit and to redundant mode routing between the first IO register circuit and a third IO register circuit such that at least certain selection circuits of the second plurality of selection circuits can be configured to select redundant mode routing rather than normal mode routing.

4. The integrated circuit of claim 3 wherein the redundant mode routing is first redundant mode routing and a selection circuit of the second plurality of selection circuits is also coupled to second redundant mode routing, the second redundant mode routing being between the first IO register circuit and a fourth IO register circuit, the selection circuit being configurable to select between the first redundant mode routing and the second redundant mode routing depending on which circuitry in the integrated circuit is defective.

5. The integrated circuit of claim 4 wherein the selection between first redundant mode routing and the second redundant mode routing depends upon whether defective circuitry is in a first row or a second row of the integrated circuit.

6. The integrated circuit of claim 2 wherein the plurality of IO register circuits include IO register circuits of different types including a first type and a second type.

7. The integrated circuit of claim 6 wherein the first type includes DQ register circuits and the second type includes DQS register circuits.

8. The integrated circuit of claim 7 wherein a first plurality of horizontal routing is coupled to respective first sets of IO register circuits, a first set including DQ register circuit and at least one DQS register circuit, and a second plurality of horizontal routing is coupled to respective second sets of IO register circuits, a second set including DQ register circuits but not any DQS register circuits.

9. The integrated circuit of claim 8 wherein some sets of IO register circuits coupled to routing for a particular row include at least a portion of one block of IO circuitry and a portion of another block of IO circuitry.

10. The integrated circuit of claim 8 further comprising a second plurality of selection circuits, a selection circuit of the second plurality of selection circuits being coupled to a DQS register circuit, to normal mode routing to first horizontal routing and to redundant mode routing to second horizontal routing such that at least certain selection circuits of the second plurality of selection circuits can be configured to select redundant mode routing rather than normal mode routing.

11. The integrated circuit of claim 1 wherein the IO buffer circuits, the IO register circuits, and the selection circuits are arranged along a top, bottom, or inner row of the integrated circuit and an IO register circuit of the plurality of IO register circuits is coupled to vertical routing to a core region or regions of the integrated circuit.

12. The integrated circuit of claim 11 further comprising a second plurality of selection circuits, a selection circuit of the second plurality of selection circuits coupled to normal mode routing between first vertical routing and a first IO register circuit and to redundant mode routing between the first vertical routing and a second IO register circuit such that if an IO register circuit is not usable, a spare IO register circuit may be utilized and at least certain selection circuits can be configured to select redundant mode routing rather than normal mode routing.

13. The integrated circuit of claim 2 further comprising:

a second plurality of input/output (IO) buffer circuits;

a second plurality of IO register circuits including spare IO register circuits; and

a second plurality of selection circuits, a selection circuit of the second plurality of selection circuits being coupled to normal mode routing between a first IO buffer circuit and a first IO register circuit and to redundant mode routing between the first IO buffer circuit and a second IO register circuit such that if an IO register circuit is not usable, a spare IO register circuit may be utilized and at least certain selection circuits can be configured to select redundant mode routing rather than normal mode routing;

wherein the second plurality of IO buffer circuits, the second plurality of IO register circuits, and the second plurality of selection circuits are arranged along a top, bottom, or inner row of the integrated circuit and an IO register circuit of the second plurality of IO register circuits is coupled to vertical routing to a core region of the integrated circuit.

14. The integrated circuit of claim 13 further comprising a third plurality of selection circuits, a selection circuit of the third plurality of selection circuits being coupled to normal mode routing between first vertical routing and a first IO register circuit of the second plurality of IO register circuits and to redundant mode routing between the first vertical routing and a second IO register circuit of the second plurality of IO register circuits such that if an IO register circuit is not usable, a spare IO register circuit may be utilized and at least certain selection circuits of the third plurality of selection circuits can be configured to select redundant mode routing rather than normal mode routing.

15. The integrated circuit of claim 1 further comprising a second plurality of selection circuits, a selection circuit of the second plurality of selection circuits being coupled to normal mode routing between first routing to a core region of the integrated circuit and a first IO register circuit of the second plurality of IO register circuits and to redundant mode routing between the first routing and a second IO register circuit of the second plurality of IO register circuits such that if an IO register circuit is not usable, a spare IO register circuit may be utilized and at least certain selection circuits of the second plurality of selection circuits can be configured to select redundant mode routing rather than normal mode routing.

16. A programmable logic device comprising the integrated circuit of claim 1.

17. A programmable logic device comprising the integrated circuit of claim 3.

18. A programmable logic device comprising the integrated circuit of claim 11.

19. A programmable logic device comprising the integrated circuit of claim 13.

20. A data processing system comprising the programmable logic device of claim 16.

21. A data processing system comprising the programmable logic device of claim 17.

22. A data processing system comprising the programmable logic device of claim 18.

23. A data processing system comprising the programmable logic device of claim 19.

24. A method of configuring an integrated circuit, the integrated circuit including repairable input/output (IO) circuitry, the method comprising:

configuring a plurality of selection circuits of the integrated circuit to select, for respective routing between a plurality of buffer circuits and a plurality of IO register circuits, either normal mode routing between a first IO buffer circuit and a first IO register circuit or redundant mode routing between the first IO buffer circuit and a second IO register circuit.

25. The method of claim 24 wherein an IO register circuit is coupled to horizontal routing and configuring is done such that selection circuits of the plurality of selection circuits that are between a defective row and a spare row are configured to select redundant mode routing.

26. The method of claim 24 wherein configuring is done such that selection circuits of the plurality of selection circuits that are coupled to IO register circuits from a defective IO register circuit to a spare IO register circuit are configured to select redundant mode routing.

27. The method of claim 24 wherein an IO register circuit is coupled to vertical routing, the method further comprising configuring a second plurality of selection circuits to select, for respective routing between the plurality of IO register circuits and a plurality of vertical routing, either normal mode routing between a first IO register circuit and first vertical routing or redundant mode routing between the first IO register and second vertical routing.

28. The method of claim 27 wherein configuring is done such that selection circuits of the plurality of selection circuits that are coupled to IO register circuits from a defective IO circuit to a spare IO circuit are configured to select redundant mode routing.

29. The method of claim 24 wherein at least some of the IO register circuits are coupled other IO register circuits of the plurality of IO register circuits, the method further comprising configuring a second plurality of selection circuits to select between normal mode routing between a first IO register circuit and a second IO register circuit and redundant mode routing between the first IO register circuit and a third IO register circuit.

30. The method of claim 29 wherein the redundant mode routing is first redundant mode routing, the method further comprising configuring the second plurality of selection circuits to select between the first redundant mode routing and second redundant mode routing, the second redundant mode routing being between the first IO register circuit and a fourth IO register circuit.

31. An integrated circuit comprising:

a plurality of input/output (IO) buffer means;

a plurality of IO register means; and

a plurality of selection means configurable to select either normal or redundant mode routing means between the IO buffer means and the IO register means.

32. The integrated circuit of claim 31 further comprising:

core routing means to rout signals from the IO register means to a core region of the integrated circuit; and

a second plurality of selection means configurable to select either normal or redundant mode routing means between the core routing means and the IO register means.

33. The integrated circuit of claim 31 further comprising:

a second plurality of selection means configurable to select either the normal or redundant mode routing means between the IO register means.