Heterogeneous labs

• US 7,902,864 B1
• Filed: 12/01/2005
• Issued: 03/08/2011
• Est. Priority Date: 12/01/2005
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Baeckler, Gregg William, Hutton, Michael D., Duwel, Keith
• Primary Examiner(s): Cho; James H.
• Assistant Examiner(s): CRAWFORD, JASON
• Application Number:
  US11/292,856
• Time in Patent Office: 1,923 Days
• Field of Search: 326 37- 41, 326/47
• US Class Current: 326/39
• CPC Class Codes: H03K 19/17728 Reconfigurable logic blocks, e.g. lookup tables
• CPC Class Codes: H03K 19/17736 Structural details of routing resources

Abstract

Disclosed is a programmable logic device (“PLD”) including at least one lookup table (“LUT”) based logic element (“LE”) of a first type and at least one LUT based LE of a second type. The first type of LE is different from the second type of LE. The term ‘different’ when used herein to describe the relationship of a first logic structure and/or its components to a second logic structure and/or its components indicates a difference in hardware design as opposed to a configuration difference or non-designed differences resulting, for example, from manufacturing variability. Additionally, a PLD can include at least one logic array block (“LAB”) of a first type having at least one LUT based LE and at least one LAB of a second type having at least one LUT based LE. The first type of LAB being different from the second type of LAB.

Claims

1. A programmable logic device (“

PLD”

) including;

at least one logic block, the one logic block including;

at least one lookup table (“

LUT”

) based logic element (“

LE”

) of a first type; and

at least one LUT based LE of a second type, wherein the first type of LE has a different hardware design from the second type of LE, wherein the first type of LE and the second type of LE reside at the same time within the PLD, wherein the first type of LE has a first number of inputs and uses less than the first number of inputs and the second type of LE has a second number of inputs and uses all of the second number of inputs, wherein each of the first and second type of LE is configured to perform arithmetic and the first type of LE is configured to perform a lower number of bits of arithmetic than the second type of LE.

2. The PLD of claim 1, wherein the first type of LE includes a lower number of registers than the second type of LE.

3. The PLD of claim 1, wherein the first type of LE includes at least a first type of LUT and the second type of LE includes at least a second type of LUT, wherein the first type of LUT includes a different number of inputs than the second type of LUT.

4. The PLD of claim 1, wherein the first type of LE is fracturable and the second type of LE is not fracturable.

5. The PLD of claim 4, wherein the first type of LE includes a first type of LUT and the second LE includes a second type of LUT, the first type of LUT having a different number of fracturable inputs than the second type of LUT.

6. The PLD of claim 1, wherein the first type of LE includes a first type of dedicated arithmetic hardware and the second type of LE includes a second type of dedicated arithmetic hardware, the first type of dedicated arithmetic hardware being different from the second type of dedicated arithmetic hardware.

7. The PLD of claim 1, wherein the first type of LE includes dedicated arithmetic hardware and the second type of LE does not include dedicated arithmetic hardware.

8. The PLD of claim 1, wherein the first type of LE receives at least one different type of secondary signal than the second type of LE.

9. The PLD of claim 1, wherein the first type of LE includes a different number of output drivers than the second type of LE.

10. The PLD of claim 1, wherein the first type of LE includes a first type of output driver and the second type of LE includes a second type of output driver wherein the first type of output driver is different from the second type of output driver.

11. The PLD of claim 1, wherein the first type of LE is implemented using a different transistor level switching implementation than the second type of LE.

12. The PLD of claim 11, wherein the first type of LE uses relatively faster transistor level switches than the second type of LE.

13. The PLD of claim 11, wherein the first type of LE uses relatively more power efficient transistor level switches than the second type of LE.

14. The PLD of claim 1, wherein the first type of LE is relatively faster than the second type of LE.

15. A programmable logic device (“

PLD”

) comprising;

at least one logic block, the one logic block including;

at least one lookup table (“

LUT”

) based logic element (“

LE”

) of a first type; and

at least one LUT based LE of a second type, wherein the first type of LE has a different hardware design from the second type of LE, wherein the first type of LE and the second type of LE reside at the same time within the PLD, wherein the first type of LE has a first number of inputs and uses less than the first number of inputs and the second type of LE has a second number of inputs and uses all of the second number of inputs, wherein the first type of LE includes a first type of register and the second type of LE includes a second type of register, the first type of register including a register cascade input and a register cascade output and the second type of LE having neither a register cascade input or a register cascade output.

16. A programmable logic device (“

PLD”

) comprising;

at least one logic block, the one logic block including;

at least one lookup table (“

LUT”

) based logic element (“

LE”

) of a first type; and

at least one LUT based LE of a second type, wherein the first type of LE has a different hardware design from the second type of LE, wherein the first type of LE and the second type of LE reside at the same time within the PLD, wherein the first type of LE has a first number of inputs and uses less than the first number of inputs and the second type of LE has a second number of inputs and uses all of the second number of inputs, wherein the first type of LE includes a ternary adder circuit and the second type of LE does not include a ternary adder circuit.

17. A programmable logic device (“

PLD”

) comprising;

at least one logic block, the one logic block including;

at least one lookup table (“

LUT”

) based logic element (“

LE”

) of a first type; and

at least one LUT based LE of a second type, wherein the first type of LE has a different hardware design from the second type of LE, wherein the first type of LE and the second type of LE reside at the same time within the PLD, wherein the first type of LE has a first number of inputs and uses less than the first number of inputs and the second type of LE has a second number of inputs and uses all of the second number of inputs, wherein;

the first type of LE includes only one register, is configured to implement only one bit of arithmetic and cannot be configured as a 4;

1 MUX; and

the second type of LE includes two registers, is configured to implement two bits of arithmetic and is configured as a 4;

1 MUX.

18. A programmable logic device (“

PLD”

) including;

at least one logic array block (“

LAB”

) of a first type having at least a first number of a first type of look up table (“

LUT”

) based logic element (“

LE”

) and a second number of a second type of LUT based LE; and

at least one LAB of a second type having at least a third number of the first type of LUT based LE and a fourth number of the second type of LUT based LE, wherein the first type of LAB is different from the second type of LAB and the first type of LUT based LE and the second type of LUT based LE have different numbers of inputs, wherein the first number does not equal the third number, wherein the second number does not equal the fourth number, wherein the first type of LAB and the second type of LAB reside at the same time within the PLD, wherein the fourth number is greater than zero, wherein the first type of LUT based LE is different from the second type of LUT based LE, wherein the first type of LUT based LE includes a first type of register and the second type of LUT based LE includes a second type of register, the first type of register including a register cascade input and a register cascade output and the second type of LUT based LE having neither a register cascade input or a register cascade output.

19. The PLD of claim 18, including at least a first column and a second column, wherein the first column includes only LABs of the first type and the second column includes only LABs of the second type.

20. The PLD of claim 18, including at least a first row and second row, wherein the first row includes only LABs of the first type and the at least second row includes only LABs of the second type.

21. The PLD of claim 18, including at least a first region and a second region, wherein the first region includes only LABs of the first type and the second region includes only LABs of the second type.

22. The PLD of claim 18, wherein the first type of LUT based LE includes a different number of registers than the second type of LUT based LE.

23. The PLD of claim 18, wherein the first type of LUT based LE includes at least a first type of LUT and the second type of LUT based LE includes at least a second type of LUT, wherein the first type of LUT, includes a different number of inputs than the second type of LUT.

24. The PLD of claim 18, wherein the first type of LUT based LE is fracturable and the second type of LUT based LE is not fracturable.

25. The PLD of claim 24, wherein the first type of LUT based LE includes a first type of LUT and the second type of LUT based LE includes a second type of LUT, the first type of LUT having a different number of fracturable inputs than the second type of LUT.

26. The PLD of claim 18, wherein the first type of LUT based LE includes a first type of dedicated arithmetic hardware and the second type of LUT based LE includes a second type of dedicated arithmetic hardware, the first type of dedicated arithmetic hardware being different from the second type of dedicated arithmetic hardware.

27. The PLD of claim 18, wherein the first type of LUT based LE includes dedicated arithmetic hardware and the second type of LUT based LE does not include dedicated arithmetic hardware.

28. The PLD of claim 18, wherein the first type of LUT based LE receives at least one different type of secondary signal than that received by the second type of LUT based LE.

29. The PLD of claim 18, wherein the first type of LUT based LE includes a different number of output drivers than the second type of LUT based LE.

30. The PLD of claim 18, wherein the first type of LUT based LE includes a first type of output driver and the second type of LUT based LE includes a second type of output driver, wherein the first type of output driver is different from the second type of output driver.

31. The PLD of claim 18, wherein the first type of LUT based LE is implemented using a different transistor level switching implementation than the second type of LUT based LE.

32. The PLD of claim 31, wherein the first type of LUT based LE uses relatively faster transistor level switches than the second type of LUT based LE.

33. The PLD of claim 31, wherein the first type of LUT based LE uses relatively more power efficient transistor level switches than the second type of LUT based LE.

34. The PLD of claim 18, wherein the first type of LUT based LE is relatively slower than the second type of LUT based LE.

35. The PLD of claim 18, wherein the first type of LAB has routed to it at least one secondary signal that is not routed to the second type of LAB.

36. The PLD of claim 18, wherein both the first type of LAB and the second type of LAB include a secondary signal generation unit and further wherein a greater number of secondary signals are routed to the secondary signal generation unit of the first type of LAB than are routed to the secondary signal generation unit of the second type of LAB.

37. The PLD of claim 18, wherein:

the first type of LAB includes a first secondary signal generation unit connectable through a first plurality of interconnections to LAB lines and local lines of the first type of LAB;

the second type of LAB includes a second secondary signal generation unit connectable through a second plurality of interconnections to LAB lines and local lines of the second type of LAB; and

wherein the number of interconnections available in the first plurality of interconnections is greater than the number of interconnections available in the second plurality of interconnections.

38. The PLD of claim 18, including a plurality of horizontal lines and vertical lines, wherein the first type of LAB is connected to a first number and type of horizontal lines and vertical lines and the second type of LAB is connected to a second number and type of horizontal lines and vertical lines.

39. The PLD of claim 18, wherein the first type of LAB has relatively greater routing flexibility than the second type of LAB.

40. A programmable logic device (“

PLD”

) comprising;

at least one logic array block (“

LAB”

) of a first type having at least a first number of a first type of look up table (“

LUT”

) based logic element (“

LE”

) and a second number of a second type of LUT based LE; and

at least one LAB of a second type having at least a third number of the first type of LUT based LE and a fourth number of the second type of LUT based LE, wherein the first type of LAB is different from the second type of LAB and the first type of LUT based LE and the second type of LUT based LE have different numbers of inputs, wherein the first number does not equal the third number, wherein the second number does not equal the fourth number, wherein the first type of LAB and the second type of LAB reside at the same time within the PLD, wherein the fourth number is greater than zero, wherein the first type of LUT based LE is different from the second type of LUT based LE, wherein the first type of LUT based LE includes a ternary adder circuit and the second type of LUT based LE does not include a ternary adder circuit.

41. A programmable logic device (“

PLD”

) comprising;

at least one logic array block (“

LAB”

) of a first type having at least a first number of a first type of look up table (“

LUT”

) based logic element (“

LE”

) and a second number of a second type of LUT based LE; and

at least one LAB of a second type having at least a third number of the first type of LUT based LE and a fourth number of the second type of LUT based LE, wherein the first type of LAB is different from the second type of LAB and the first type of LUT based LE and the second type of LUT based LE have different numbers of inputs, wherein the first number does not equal the third number, wherein the second number does not equal the fourth number, wherein the first type of LAB and the second type of LAB reside at the same time within the PLD, wherein the fourth number is greater than zero, wherein the first type of LUT based LE is different from the second type of LUT based LE, wherein;

the first type of LE includes only one register, is configured to implement only one bit of arithmetic and cannot be configured as a 4;

1 MUX; and

the second type of LE includes two registers, is configured to implement two bits of arithmetic and is configured as a 4;

1 MUX.

42. A programmable logic device (PLD) comprising:

at least one logic array block (“

LAB”

) of a first type having at least a first number of a first type of look up table (“

LUT”

) based logic element (“

LE”

) and a second number of a second type of LUT based LE; and

at least one LAB of a second type having at least a third number of the first type of LUT based LE and a fourth number of the second type of LUT based LE, wherein the first type of LAB is different from the second type of LAB and the first type of LUT based LE and the second type of LUT based LE have different numbers of inputs, wherein the first number does not equal the third number, wherein the second number does not equal the fourth number, wherein the first type of LAB and the second type of LAB reside at the same time within the PLD, wherein the fourth number is greater than zero, wherein the first type of LAB includes power down circuitry and the second type of LAB does not include power down circuitry.

43. A programmable logic device (“

PLD”

) comprising;

at least one logic block, the one logic block including;

at least one lookup table (“

LUT”

) based logic element (“

LE”

) of a first type; and

at least one LUT based LE of a second type, wherein the first type of LE has a different hardware design from the second type of LE, wherein the first type of LE and the second type of LE reside at the same time within the PLD, wherein each of the first and second type of LE is configured to perform arithmetic and the first type of LE is configured to perform a lower number of bits of arithmetic than the second type of LE.

44. The PLD of claim 43, wherein the first type of LE includes at least a first type of LUT and the second type of LE includes at least a second type of LUT, wherein the first type of LUT includes a different number of inputs than the second type of LUT.

45. The PLD of claim 43, wherein the first type of LE is fracturable and the second type of LE is not fracturable.