Wires on demand: run-time communication synthesis for reconfigurable computing

• US 7,902,866 B1
• Filed: 08/27/2008
• Issued: 03/08/2011
• Est. Priority Date: 08/27/2007
• Status: Expired due to Fees

• Current Assignee: Luna Innovations, Inc., Virginia Tech Intellectual Properties, Inc. (Virginia Polytechnic Institute and State University)
• Original Assignee: Virginia Tech Intellectual Properties, Inc. (Virginia Polytechnic Institute and State University)
• Inventors: Rice, Justin D., Graf, Jonathan, Dunham, Timothy G., Patterson, Cameron, Shelburne, Matthew T., Bowen, John K., Pletri, Jorge A. Suris, Athanas, Peter
• Primary Examiner(s): Le; Don P
• Application Number:
  US12/199,465
• Time in Patent Office: 923 Days
• Field of Search: 326 37- 41
• US Class Current: 326/41
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]

Abstract

A method, and system, for reconfiguring an FPGA which has a static region and a dynamic region is provided. The method includes the steps of: (a) providing a dynamic module library having information of predetermined modules; (b) receiving a reconfiguration request external to the FPGA; (c) computing reconfiguration of the FPGA at a predetermined location using predetermined module information from the dynamic module library and the reconfiguration request, and generating reconfigurable partial bitstreams; and (d) sending partial bitstreams from the predetermined location to the FPGA to perform the reconfiguration.

Claims

1. A method for reconfiguring an FPGA which has a static region and a dynamic region, the method comprising:

(a) receiving an FPGA reconfiguration request at a server located externally of the FPGA;

(b) computing reconfiguration of the FPGA at the server, using the request and information of predetermined modules; and

(c) sending partial bitstreams from the server to the FPGA to reconfigure the FPGA;

wherein the dynamic region is configured such that the modules to be located in the dynamic region are not constrained to lie within regions defined within the dynamic region, but instead may be placed as resources in the dynamic region allow.

2. The method of claim 1, further comprising:

(d) providing a dynamic module library having the predetermined module information.

3. The method of claim 2, wherein step (d) of providing the dynamic module library is performed during compile time;

and step (b) of computing the reconfiguration is performed during run time.

4. A method for reconfiguring an FPGA which has a static region and a dynamic region, the method comprising:

(a) receiving an FPGA reconfiguration request at a server located externally of the FPGA;

(b) computing reconfiguration of the FPGA at the server, using the request and information of predetermined modules; and

(c) sending partial bitstreams from the server to the FPGA to reconfigure the FPGA;

wherein step (b) of computing the reconfiguration comprises;

(b-1) selecting a list of modules using the predetermined module information;

(b-2) determining placement of the modules in the dynamic region of the FPGA using the list of selected modules and the reconfiguration request;

(b-3) determining connections among the selected modules;

(b-4) determining channel routing between the selected modules in the dynamic region and the static region;

(b-5) generating the reconfigurable partial bitstreams using information generated from steps (b-2), (b-3) and (b-4).

5. The method of claim 4, wherein the partial bitstreams perform placement of the selected modules inside the dynamic region of the FPGA, interconnect the modules, and create channel routing between the static region and the dynamic region.

6. A method for reconfiguring an FPGA which has a static region and a dynamic region, the method comprising:

(a) providing a dynamic module library storing predetermined modules;

(b) receiving a reconfiguration request external to the FPGA;

(c) computing reconfiguration of the FPGA at a predetermined location using the reconfiguration request and the predetermined module information from the dynamic module library, and generating reconfigurable partial bitstreams; and

(d) sending partial bitstreams from the predetermined location to the FPGA to perform the reconfiguration;

wherein the dynamic region is configured such that the modules to be located in the dynamic region are not constrained to lie within regions defined within the dynamic region, but instead may be placed as resources in the dynamic region allow.

7. The method of claim 6, wherein the dynamic module library is created at compile time;

and wherein step (c) is performed during run time of the FPGA.

8. The method of claim 7, wherein the predetermined location is a dynamic module server.

9. The method of claim 6, wherein step (c) comprises:

(c-1) retrieving a list of datapaths available in the FPGA;

(c-2) selecting modules from the predetermined modules for the reconfiguration; and

(c-3) determining placement and connections of the selected modules in the datapaths.

10. The method of claim 9, wherein the predetermined location comprises an interface for receiving the reconfiguration request and for sending the partial bitstreams to the FPGA.

11. A method for reconfiguring an FPGA which has a static region and a dynamic region, the method comprising:

(a) providing a dynamic module library storing predetermined modules;

(b) receiving a reconfiguration request external to the FPGA;

(c) computing reconfiguration of the FPGA at a predetermined location using the reconfiguration request and the predetermined module information from the dynamic module library, and generating reconfigurable partial bitstreams; and

(d) sending partial bitstreams from the predetermined location to the FPGA to perform the reconfiguration;

wherein the dynamic module library comprises a plurality of wrapper module structures, each module having a pre-processed module, a plurality of multiplexers, and a plurality of input and output ports, wherein the pre-processed module, the multiplexers and the input and output ports are interconnected.

12. A dynamic module system for reconfiguring an FPGA which has a static region and a dynamic region, comprising:

an interface for receiving a reconfiguration request;

a manager for receiving the reconfiguration request and information of predetermined modules, and determining placement and connections of modules inside the dynamic region of the FPGA; and

a bitstream toolbox connected to the manager and generating a reconfigurable partial bitstream to the FPGA via the interface;

wherein the manager is configured such that the modules to be located in the dynamic region are not constrained to lie within regions defined within the dynamic region, but instead may be placed as resources in the dynamic region allow.

13. The dynamic module system of claim 12, wherein the manager comprises:

a datapath manager for determining the placement of the modules; and

a channel routing manager for determining the connections of the modules.

14. The dynamic module system of claim 13, wherein the datapath manager further receives bitstreams that define configuration of the static region in the FPGA.

15. A dynamic module system for reconfiguring an FPGA which has a static region and a dynamic region, comprising:

an interface for receiving a reconfiguration request;

a manager for receiving the reconfiguration request and information of predetermined modules, and determining placement and connections of modules inside the dynamic region of the FPGA;

a bitstream toolbox connected to the manager and generating a reconfigurable partial bitstream to the FPGA via the interface; and

a reconfigurable supervisor connected between the interface and the datapath manager, the reconfigurable supervisor receiving the reconfiguration request from the interface and the predetermined module information, and generating a module request to the datapath manager;

wherein the manager comprises;

a datapath manager for determining the placement of the modules; and

a channel routing manager for determining the connections of the modules; and

wherein the datapath manager further receives bitstreams that define configuration of the static region in the FPGA.

16. The dynamic module system of claim 15, wherein the reconfigurable supervisor further receives information regarding dimensions and resources of the dynamic region of the FPGA.

17. The dynamic module system of claim 16, wherein the datapath manager comprises a placer for selecting modules for the dynamic region from the predetermined module information and determining placement and connections of the selected modules.

18. The dynamic module system of claim 17, wherein the placer further receives physical annotation information of the selected modules.

19. The dynamic module system of claim 18, wherein the datapath manager further comprises a router connected to the placer and generating interconnecting information to the bitstream toolbox.