Clock gating system and method

• US 7,902,878 B2
• Filed: 04/29/2009
• Issued: 03/08/2011
• Est. Priority Date: 04/29/2008
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Saint-Laurent, Martin, Mohd, Bassam Jamil, Bassett, Paul
• Primary Examiner(s): Tan; Vibol
• Application Number:
  US12/431,992
• Publication Number:
  US 20090267649A1
• Time in Patent Office: 678 Days
• Field of Search: 326/93, 326/95, 326/98, 327200-218, 327/291, 327/298, 327/365, 327/379
• US Class Current: 326/98
• CPC Class Codes: G06F 1/04 Generating or distributing clock signals or signals derived directly therefrom
• CPC Class Codes: H03K 19/0016 by using a control or a clock signal, e.g. in order to apply power supply

Abstract

A clock gating system and method is disclosed. In a particular embodiment, the system includes an input logic circuit having at least one input to receive at least one input signal and having an output at an internal enable node. A keeper circuit includes at least one switching element that is responsive to a gated clock signal and is coupled to the internal enable node to selectively hold a logical voltage level at the internal enable node. The system further includes a gating element responsive to an input clock signal and to the logical voltage level at the internal enable node to generate the gated clock signal.

Claims

1. A clock gating circuit comprising:

an input logic circuit having at least one input to receive at least one input signal and having an output coupled to an internal enable node, wherein the input logic circuit includes a pullup circuit serially coupled via the internal enable node to a pulldown circuit, and further comprising;

a first isolation element configured to selectively prevent the pullup circuit from biasing the internal enable node at a logical high voltage level; and

a second isolation element configured to selectively prevent the pulldown circuit from biasing the internal enable node at a logical low level, wherein at least one of the first isolation element and the second isolation element is responsive to a gated clock signal;

a keeper circuit coupled to selectively hold a logical voltage level at the internal enable node, the keeper circuit including at least one switching element that is responsive to the gated clock signal; and

a gating element responsive to an input clock signal and to the logical voltage level at the internal enable node to generate the gated clock signal.

2. The clock gating circuit of claim 1, wherein the keeper circuit includes a keeper isolation element configured to prevent a logical voltage level change at the internal enable node due to a current flow through the keeper circuit during a delay period associated with the gating element when the input clock signal transitions.

3. The clock gating circuit of claim 1, wherein less than nine transistors toggle with each input clock signal transition.

4. The clock gating circuit of claim 1, wherein the keeper circuit comprises:

a p-channel metal-oxide-semiconductor (PMOS) transistor having a first terminal coupled to a supply, a control terminal coupled to receive the gated clock signal, and a second terminal coupled to an input logic isolation element;

a first n-channel metal-oxide-semiconductor (NMOS) transistor having a first terminal coupled to the second terminal of the PMOS transistor;

an inverter having an input coupled to the second terminal of the PMOS transistor and further having an output coupled to a control terminal of the first NMOS transistor; and

a second NMOS transistor having a first terminal coupled to the first NMOS transistor and having a second terminal coupled to a ground, wherein a control terminal of the second NMOS transistor is coupled to receive the input clock signal.

5. The clock gating circuit of claim 1, wherein the first terminal of the first NMOS transistor is coupled to the second terminal of the PMOS transistor via the input logic isolation element.

6. The clock gating circuit of claim 1, wherein the keeper circuit comprises:

a p-channel metal-oxide-semiconductor (PMOS) transistor having a first terminal coupled to a supply, a control terminal coupled to receive the gated clock signal, and a second terminal coupled to an input logic isolation element; and

an n-channel metal-oxide-semiconductor (NMOS) transistor having a first terminal coupled to the second terminal of the PMOS transistor via the input logic isolation element and having a second terminal coupled to a ground, wherein a control terminal of the NMOS transistor is coupled to receive the input clock signal.

7. A system comprising:

a NAND logic circuit having a first input coupled to receive a clock signal and having an output coupled to provide a gated clock signal; and

a keeper circuit coupled to provide an enable signal to a second input of the NAND logic circuit, wherein less than nine transistors but not less than four transistors toggle with each clock signal transition, wherein the keeper circuit comprises;

a p-channel metal-oxide-semiconductor (PMOS) transistor having a first terminal coupled to a supply and having a control terminal coupled to receive the gated clock signal;

a first n-channel metal-oxide-semiconductor (NMOS) transistor having a first terminal responsive to a second terminal of the PMOS transistor;

an inverter having an input coupled to the second terminal of the PMOS transistor and further having an output coupled to a control terminal of a first NMOS transistor; and

a second NMOS transistor having a first terminal coupled to the first NMOS transistor and having a second terminal coupled to ground, wherein a control terminal of the second NMOS transistor is coupled to receive the clock signal.

8. The system of claim 7, wherein the second terminal of the PMOS transistor is coupled to an input logic isolation element,

and wherein the first terminal of the first NMOS transistor is coupled to the second terminal of the PMOS transistor via the input logic isolation element.

9. The system of claim 7, wherein the NAND logic circuit and the keeper circuit are included in a communications device or a computer into which the system is integrated.

10. An apparatus comprising:

input logic means for receiving at least one input signal and providing an output coupled to an internal enable node;

keeper means for selectively holding a logical voltage level at the internal enable node, the keeper means including at least one switching element that is responsive to a gated clock signal, wherein the keeper means comprises;

first means for switching having a first terminal coupled to a supply and having a control terminal coupled to receive the gated clock signal;

second means for switching having a first terminal coupled to a second terminal of the first means for switching;

means for inverting having an input coupled to the second terminal of the first means for switching and further having an output coupled to a control terminal of the first means for switching; and

third means for switching having a first terminal coupled to the first means for switching and having a second terminal coupled to ground, wherein a control terminal of the second means for switching is coupled to receive the input clock signal; and

gating means for generating the gated clock signal, wherein the gating means is responsive to an input clock signal and to the logical voltage level at the internal enable node.

11. The apparatus of claim 10 integrated in a system-on-chip device.

12. The apparatus of claim 10, wherein the apparatus is a semiconductor device integrated into a communications device or a computer.

13. A method comprising:

receiving at least one input signal at an input logic circuit having at least one input and having an output coupled to an internal enable node;

generating a gated clock signal at a gating element that is responsive to an input clock signal and to a logical voltage level at the internal enable node;

selectively holding the logical voltage level at the internal enable node in response to the gated clock signal; and

selecting one of a first clock gating cell having a first keeper circuit and a second clock gating cell having a second keeper circuit based on at least one design criterion, wherein the first clock gating cell includes fewer transistors that toggle with each input clock signal toggle than the second clock gating cell, and wherein the first keeper circuit comprises;

a first field effect transistor (FET) having a first terminal coupled to a supply and having a control terminal coupled to receive the gated clock signal;

a second FET having a first terminal coupled to a second terminal of the first FET via an input logic isolation element;

an inverter having an input coupled to the second terminal of the first FET and further having an output coupled to a control terminal of the second FET; and

a third FET having a first terminal coupled to the second FET and having a second terminal coupled to ground, wherein a control terminal of the third FET is coupled to receive the input clock signal.

14. The method of claim 13, wherein receiving the at least one input signal, selectively holding the logical voltage level, and generating the gated clock signal are performed at a processor integrated into an electronic device.

15. The method of claim 13, wherein the at least one design criterion includes power consumption.

16. The method of claim 13, wherein the at least one design criterion includes speed of operation.

17. The method of claim 13, wherein the at least one design criterion includes an area of the first clock gating cell or an area of the second clock gating cell.

18. The method of claim 13, wherein the first clock gating cell includes not more than four transistors that toggle in response to each input clock signal toggle.

19. The method of claim 13, wherein fewer than half of the transistors of the first keeper circuit toggle in response to each input clock signal toggle.

20. The method of claim 13, wherein the first FET comprises a p-channel metal-oxide-semiconductor (PMOS) transistor, wherein the second FET comprises a first n-channel metal-oxide-semiconductor (NMOS) transistor, and where the third FET comprises a second NMOS transistor.

21. The method of claim 13, wherein the first terminal of the second FET is coupled to a second terminal of the first FET via an input logic isolation element.

22. A system comprising:

an input logic circuit of a clock gating cell, the input logic having at least one input to receive at least one input signal and having an output coupled to an internal enable node; and

a keeper circuit of the clock gating cell coupled to selectively hold a logical voltage level at the internal enable node, the keeper circuit including at least one switching element that is responsive to a gated clock signal generated at the clock gating cell, wherein the clock gating cell includes not more than four transistors that toggle with each transition of an input clock signal, and wherein the keeper circuit comprises;

a p-channel metal-oxide-semiconductor (PMOS) transistor having a first terminal coupled to a supply and having a control terminal coupled to receive the gated clock signal;

a first n-channel metal-oxide-semiconductor (NMOS) transistor having a first terminal coupled to a second terminal of the PMOS transistor;

an inverter having an input coupled to the second terminal of the PMOS transistor and further having an output coupled to a control terminal of the first NMOS transistor; and

a second NMOS transistor having a first terminal coupled to the first NMOS transistor and having a second terminal coupled to ground, wherein a control terminal of the second NMOS transistor is coupled to receive the input clock signal.

23. A clock gating circuit comprising:

an input logic circuit having at least one input to receive at least one input signal and having an output coupled to an internal enable node;

a keeper circuit coupled to selectively hold a logical voltage level at the internal enable node, the keeper circuit including at least one switching element that is responsive to a gated clock signal; and

a gating element responsive to an input clock signal and to the logical voltage level at the internal enable node to generate the gated clock signal;

wherein the keeper circuit includes a keeper isolation element configured to prevent a logical voltage level change at the internal enable node due to a current flow through the keeper circuit during a delay period associated with the gating element when the input clock signal transitions.

24. A clock gating circuit comprising:

an input logic circuit having at least one input to receive at least one input signal and having an output coupled to an internal enable node;

a keeper circuit coupled to selectively hold a logical voltage level at the internal enable node, the keeper circuit including at least one switching element that is responsive to a gated clock signal, wherein the keeper circuit comprises;

a p-channel metal-oxide-semiconductor (PMOS) transistor having a first terminal coupled to a supply, a control terminal coupled to receive the gated clock signal, and a second terminal coupled to an input logic isolation element;

a first n-channel metal-oxide-semiconductor (NMOS) transistor responsive to the PMOS transistor;

an inverter having an input coupled to the PMOS transistor and further having an output coupled to a control terminal of the first NMOS transistor; and

a second NMOS transistor having a first terminal coupled to the first NMOS transistor and having a second terminal coupled to ground, wherein a control terminal of the second NMOS transistor is coupled to receive the input clock signal; and

a gating element responsive to an input clock signal and to the logical voltage level at the internal enable node to generate the gated clock signal.

25. A clock gating circuit comprising:

an input logic circuit having at least one input to receive at least one input signal and having an output coupled to an internal enable node;

a keeper circuit coupled to selectively hold a logical voltage level at the internal enable node, the keeper circuit including at least one switching element that is responsive to a gated clock signal, wherein the keeper circuit comprises;

a p-channel metal-oxide-semiconductor (PMOS) transistor having a first terminal coupled to a supply, a control terminal coupled to receive the gated clock signal, and a second terminal coupled to an input logic isolation element; and

an n-channel metal-oxide-semiconductor (NMOS) transistor having a first terminal responsive to the second terminal of the PMOS transistor and responsive to the input logic isolation element and having a second terminal coupled to a ground, wherein a control terminal of the NMOS transistor is coupled to receive the input clock signal; and

a gating element responsive to an input clock signal and to the logical voltage level at the internal enable node to generate the gated clock signal.