Method and apparatus for tuning phase of clock signal
First Claim
1. A semiconductor memory apparatus configured to employ a data clock signal that has a different frequency than a main clock signal, the semiconductor memory apparatus comprising:
- a clock signal receiver configured to receive the main clock signal and the data clock signal from a memory controller; and
a phase tuner configured to;
during coarse tuning, generate a frequency-divided clock signal having a same frequency as the main clock signal by dividing a frequency of the data clock signal,during the coarse tuning, generate from the frequency-divided clock signal at least four multiphase frequency-divided clock signals having the same frequency as the frequency-divided clock signal and different phases from one another,during the coarse tuning, compare each phase of the at least four multiphase frequency-divided clock signals with a phase of the main clock signal,during the coarse tuning, feed back each comparison result to the memory controller, andduring fine tuning, compare a phase of a signal selected from the at least four multiphase frequency-divided clock signals with the phase of the main clock signal and feed back a comparison result to the memory controller.
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Abstract
A method and apparatus for tuning a phase of a data clock signal having a different frequency than a main clock signal. The method of tuning includes coarse tuning by receiving the data clock signal, dividing the data clock signal to generate a frequency-divided clock signal having a same frequency as the main clock signal, repeatedly shifting the frequency-divided clock signal to generate multiphase frequency-divided clock signals at a predetermined phase interval, comparing a phase of each of the multiphase frequency-divided clock signals with a phase of the main clock signal, and determining a phase shift amount based on a comparison result, and fine tuning by comparing a phase of a multiphase frequency-divided clock signal corresponding to the phase shift amount with the phase of the main clock signal and adjusting the phase of the data clock signal by a predetermined phase step based on the comparison result.
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Citations
20 Claims
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1. A semiconductor memory apparatus configured to employ a data clock signal that has a different frequency than a main clock signal, the semiconductor memory apparatus comprising:
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a clock signal receiver configured to receive the main clock signal and the data clock signal from a memory controller; and a phase tuner configured to; during coarse tuning, generate a frequency-divided clock signal having a same frequency as the main clock signal by dividing a frequency of the data clock signal, during the coarse tuning, generate from the frequency-divided clock signal at least four multiphase frequency-divided clock signals having the same frequency as the frequency-divided clock signal and different phases from one another, during the coarse tuning, compare each phase of the at least four multiphase frequency-divided clock signals with a phase of the main clock signal, during the coarse tuning, feed back each comparison result to the memory controller, and during fine tuning, compare a phase of a signal selected from the at least four multiphase frequency-divided clock signals with the phase of the main clock signal and feed back a comparison result to the memory controller. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A memory system using a data clock signal that has a different frequency than a main clock signal, the memory system comprising:
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a first memory apparatus configured to; receive the data clock signal, divide a frequency of the data clock signal to generate a first frequency-divided clock signal having the same frequency as the main clock signal, repeatedly shift the first frequency-divided clock signal to generate at least four multiphase frequency-divided clock signals at a predetermined phase interval, which have a same frequency as and different phases than the first frequency-divided clock signal, and compare a phase of each of the at least four multiphase frequency-divided clock signals with a phase of the main clock signal, and output a comparison result; and a memory controller configured to transmit the main clock signal and the data clock signal to the first memory apparatus, receive the comparison result from the first memory apparatus, and select one signal from the at least four multiphase frequency-divided clock signals based on the comparison result, wherein the first memory apparatus compares a phase of the selected multiphase frequency-divided clock signal with the phase of the main clock signal and feeds back a comparison result to the memory controller, and wherein the memory controller adjusts a phase of the data clock signal by a predetermined phase step based on the comparison result fed back from the first memory apparatus and transmits a phase-adjusted data clock signal to the first memory apparatus. - View Dependent Claims (12, 13, 14, 15, 16)
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17. A method of tuning a phase of a data clock signal that has a different frequency than a main clock signal, the method comprising:
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coarse tuning by receiving the data clock signal, dividing the data clock signal to generate a frequency-divided clock signal having a same frequency as the main clock signal, repeatedly shifting the frequency-divided clock signal to generate at least four multiphase frequency-divided clock signals at a predetermined phase interval, which have the same frequency as and different phases than the frequency-divided clock signal, comparing a phase of each of the at least four multiphase frequency-divided clock signals with a phase of the main clock signal, and selecting one signal from the at least four multiphase frequency-divided clock signals based on a comparison result; and fine tuning by comparing a phase of the selected multiphase frequency-divided clock signal with the phase of the main clock signal and adjusting the phase of the data clock signal by a predetermined phase step based on the comparison result. - View Dependent Claims (18, 19, 20)
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Specification