Bias current generator

• US 7,902,912 B2
• Filed: 03/25/2008
• Issued: 03/08/2011
• Est. Priority Date: 03/25/2008
• Status: Expired due to Fees

• Current Assignee: Analog Devices, Inc.
• Original Assignee: Analog Devices, Inc.
• Inventors: Marinca, Stefan
• Primary Examiner(s): TRA, ANH QUAN
• Application Number:
  US12/054,909
• Publication Number:
  US 20090243711A1
• Time in Patent Office: 1,078 Days
• Field of Search: 327/539, 327512-513, 323/313, 323/315
• US Class Current: 327/539
• CPC Class Codes: G05F 3/30 Regulators using the difference between the base-emitter voltages of two bipolar transistors operating at different current densities G05F3/26 takes precedence

Abstract

A bias current generator for generating bias current is described. The generator comprises an amplifier having an inverting input, a non-inverting input and an output. A first bipolar transistor is associated with one of the inverting and non-inverting inputs of the amplifier. A load MOS device is associated with the other one of the inverting and non-inverting inputs of the amplifier. The load MOS device is driven by the amplifier to operate in the triode region with a corresponding drain-source resistance r_on. The first bipolar transistor and the load MOS device are arranged such that a voltage derived from the first bipolar transistor is developed across the drain-source resistance r_on of the load MOS device thereby generating a bias current.

Claims

1. A bias current generator comprising:

a first amplifier having an inverting input, a non-inverting input and an output;

a first bipolar transistor having a base-emitter voltage associated with a first one of the inverting or non-inverting inputs of the first amplifier;

a load MOS transistor comprising a gate, a source, and a drain, wherein the load MOS transistor is associated with a second one of the inverting or non-inverting inputs of the first amplifier, wherein the gate of the load MOS transistor is operatively coupled to the output of the first amplifier;

a second bipolar transistor operating at a lower collector current density than that of the first bipolar transistor, wherein a base-emitter voltage of the second bipolar transistor is also associated with the second one of the inverting or non-inverting inputs of the first amplifier such that the base-emitter voltage of the second bipolar transistor is arranged in series with a drain-source voltage of the load MOS transistor; and

a biasing MOS transistor associated with the load MOS transistor, wherein the gate of the biasing MOS transistor is operatively coupled to the output of the first amplifier such that a gate to source voltage of the load MOS transistor and a gate to source voltage of the biasing MOS transistor are the same;

wherein the first amplifier, the first bipolar transistor, the second bipolar transistor, the load MOS transistor, and the biasing MOS transistor are arranged in a feedback loop such that the biasing MOS transistor is biased to operate in the saturation region and the load MOS transistor is biased to operate in the triode region;

wherein the first and second bipolar transistors are arranged relative to the load MOS transistor such that operation of the feedback loop develops a voltage across the drain-source resistance r_on of the load MOS transistor equivalent to the base-emitter voltage difference Δ

V_be between the first bipolar transistor and the second bipolar transistor thereby generating a PTAT bias current.

2. A bias current generator as claimed in claim 1, wherein the bias current generator further comprises a current mirror arrangement driven by the first amplifier for mirroring the generated bias current.

3. A bias current generator as claimed in claim 2, wherein the current mirror arrangement comprises a plurality of PMOS devices.

4. A bias current generator as claimed in claim 1, wherein the load MOS transistor and the biasing MOS transistor have different aspect ratios.

5. A bias current generator as claimed in claim 4, wherein the aspect ratio of the load MOS transistor is greater than the aspect ratio of the biasing MOS transistor.

6. A bias current generator comprising:

a first amplifier having an inverting input, a non-inverting input and an output;

a first bipolar transistor having a emitter, a base, and a collector, wherein the base is electrically coupled to a first voltage reference, wherein the collector is electrically coupled to a second voltage reference, and wherein the emitter is electrically coupled to the inverting input of the first amplifier;

a second bipolar transistor having an emitter, a base, and a collector, wherein the collector is electrically coupled to the second voltage reference, and wherein the emitter is electrically coupled to the non-inverting input of the amplifier;

a load MOS transistor having a gate, a source, and a drain, wherein the gate is electrically coupled to the output of the first amplifier, wherein the source is electrically coupled to the first voltage reference, and wherein the drain is electrically coupled to the base of the second bipolar transistor;

a biasing MOS transistor having a gate, a source, and a drain, wherein the gate is electrically coupled to the output of the first amplifier, and wherein the source is electrically coupled to the first voltage reference, and wherein the drain is electrically coupled to a first node;

a diode connected MOS transistor having a gate, a source, and a drain, wherein the gate and the drain are electrically coupled to the first node, and wherein the source is electrically coupled to third voltage reference;

a first mirror MOS transistor having a gate, a source, and a drain, wherein the gate is electrically coupled to the first node, wherein the source is electrically coupled to the third voltage reference, and wherein the drain is electrically coupled to the emitter of the first bipolar transistor;

a second mirror MOS transistor having a gate, a source, and a drain, wherein the gate is electrically coupled to the first node, wherein the source is electrically coupled to the third voltage reference, and wherein the drain is electrically coupled to the emitter of the second bipolar transistor; and

a third mirror MOS transistor having a gate, a source, and a drain, wherein the gate is electrically coupled to the first node, wherein the source is electrically coupled to the third voltage reference, and wherein the drain is electrically coupled to the base of the second bipolar transistor.

7. The bias current generator of claim 6, wherein the load MOS transistor has an aspect ratio greater than an aspect ratio of the biasing MOS transistor.

8. The bias current generator of claim 6, wherein the second bipolar transistor is configured to operate at a lower collector-current density than that of the first bipolar transistor.