Delta-sigma analog-to-digital converter (ADC) having a serialized quantizer output

• US 7,903,010 B1
• Filed: 08/31/2009
• Issued: 03/08/2011
• Est. Priority Date: 08/31/2009
• Status: Active Grant

• Current Assignee: Cirrus Logic Incorporated
• Original Assignee: Cirrus Logic Incorporated
• Inventors: Melanson, John L.
• Primary Examiner(s): WILLIAMS, HOWARD L
• Application Number:
  US12/551,198
• Publication Number:
  US 20110050472A1
• Time in Patent Office: 554 Days
• Field of Search: 341/76, 341/77, 341/100, 341/101, 341/143, 341/155
• US Class Current: 341/143
• CPC Class Codes: H03M 3/424 the quantiser being a multiple bit one
• CPC Class Codes: H03M 3/474 using time-division multiplexing

Abstract

A delta-sigma analog-to-digital converter (ADC) having a serialized quantizer output has a data rate greater than a quantization rate of the delta-sigma modulator, but less than a bit rate determined by the product of the number of bits required to represent the input to a feedback digital-to-analog converter and the quantization rate. Additional information can be encoded in the serial bit stream by selection among redundant codes based on the value of the additional information. The serial bit stream may encode differences between successive quantizer output samples and the additional information may include the absolute value of the quantizer output, synchronization information and/or framing information for distinguishing data corresponding to multiple ADC input channels.

Claims

1. An analog-to-digital converter, comprising:

a noise-shaping filter having an input for receiving an analog signal to be converted to a digital value;

a quantizer having an input coupled to an output of the noise-shaping filter for generating quantized output values at a quantization rate of the quantizer, wherein the quantized output values are from a set of more than two output values;

a digital-to-analog converter having an input for receiving the quantized output values and having an output coupled to an input of the noise-shaping filter for providing a feedback signal, wherein the noise-shaping filter, the quantizer and the digital-to-analog converter form a delta-sigma modulator loop; and

a serial data circuit having an input coupled to an output of the quantizer for generating a serial bit stream representing the quantized output values, wherein a ratio of the bit rate of the serial bit stream to the quantization rate of the quantizer is greater than unity but less than a minimum number of bits required to represent the input of the digital-to-analog converter.

2. The analog-to-digital converter of claim 1, wherein the serial data circuit generates the serial bit stream to encode differences between sequential values of the output of the quantizer at the quantization rate of the quantizer.

3. The analog-to-digital converter of claim 1, wherein the quantizer generates constrained output values such that the serial data circuit encodes the bitstream to represent the quantized output values with a set of codes smaller than the number of codes available in the serial bit stream, whereby additional information is embedded in the serial bit stream by selection among two or more redundant codes both indicating a same next quantized output value, but different values for the additional information.

4. The analog-to-digital converter of claim 3, wherein the serial data circuit generates the serial bit stream to encode differences between sequential values of the output of the quantizer at the quantization rate of the quantizer and wherein the serial bit stream encodes the additional information including an indication of an absolute level of the output of the quantizer encoded over multiple frames of the serial bit stream.

5. The analog-to-digital converter of claim 3, wherein the serial bit stream encodes the additional information including synchronization information indicating the position of frames of the quantized output values within the serial bit stream.

6. The analog-to-digital converter of claim 3, wherein the quantizer is a first quantizer, wherein the quantized output values are first quantized output values, wherein the analog-to-digital converter includes a second delta-sigma modulator loop generating an output from a second quantizer, and having a second input provided to a second noise-shaping filter of the second delta-sigma modulator loop, wherein the serial bit stream encodes the first and the second quantized output values, and wherein the serial bit stream further encodes the additional information including a framing indication for indicating whether a given quantized output value in the serial bit stream is one of the first quantized output values or one of the second quantized output values.

7. The analog-to-digital converter of claim 6, wherein the second quantized output values are generated at a second quantization rate that differs from the quantization rate of the first quantizer.

8. The analog-to-digital converter of claim 3, wherein the serial bit stream encodes a set of differences between sequential ones of the quantized output values including only a single bit increment, a single bit decrement, and no change, and wherein the serial bit stream encodes a first set of codes for each of the elements of the set of differences and a second code representing a particular element of the set of differences in addition to the corresponding particular one of first codes that represents the particular element, and wherein the serial data circuit encodes the additional information in a pattern formed by generation of the particular one of the first codes and the second codes when the value of the output of the quantizer is equal to the particular element of the set of differences.

9. The analog-to-digital converter of claim 1, wherein the serial bit stream is a two bit code generated at the quantization rate of the quantizer and representing three values of the output of the quantizer.

10. The analog-to-digital converter of claim 1, further comprising:

a transformer having a first winding coupled to an output of the serial data circuit; and

a decoder circuit having an input coupled to a second winding of the transformer, wherein the decoder circuit decodes the serial bit stream to obtain the quantized output values.

11. The analog-to-digital converter of claim 10, further comprising a power supply circuit for receiving at least one of a power supply voltage for operating the analog-to-digital converter or a clock signal for operating the quantizer from the first winding of the transformer.

12. The analog-to-digital converter of claim 1, further comprising a digital integrator having an input coupled to an output of the quantizer for integrating the quantized output values, wherein the feedback signal is provided from the output of the digital integrator.

13. The analog-to-digital converter of claim 12, wherein the quantizer generates constrained output values such that the serial data circuit encodes the differences with a set of codes smaller than the number of codes available in the serial bit stream, and wherein the serial data circuit further embeds a value of the output of the digital integrator in the serial bit stream by selection among two or more redundant codes both representing a particular output level of the quantizer.

14. An analog-to-digital converter, comprising:

a quantizer for generating a digital output from an analog input signal; and

an output encoder for generating a data output of the analog-to-digital converter from the digital output of the quantizer, wherein the data output represents changes in the digital output as a sequence of codes in the data output, and wherein the sequence of codes extends over a set of codes including at least one redundant code, whereby one value of the changes in the digital output is represented by at least two codes, and wherein a pattern of the at least two codes in the data output represents an indication of an absolute level of the digital output.

15. A decoder circuit for receiving and decoding a serial bit stream representing output values of an analog-to-digital conversion, the decoder circuit comprising:

a receiver for receiving the serial bit stream, wherein the serial bit stream encodes the output values of the analog-to-digital conversion along with additional information by using redundant codes to express at least one output level of the analog-to-digital conversion; and

a decoder for decoding the serial bit stream to obtain the output values, wherein the decoder checks a sequence of codes within the serial bit stream for error by examining a sequence of the redundant codes.

16. The decoder circuit of claim 15, wherein the serial bit stream encodes changes in an output of a quantizer that performs the analog-to-digital conversion, wherein the additional information represents an absolute level of the output of the quantizer, wherein the decoder further obtains the absolute level of the output of the quantizer from the serial bit stream.

17. The decoder circuit of claim 15, wherein the serial bit stream represents oversampled values of the analog-to-digital conversion and wherein the decoder circuit further comprises a decimation filter having an input coupled to an output of the decoder for generating an output from the oversampled values.

18. A method of operating an analog-to-digital converter, comprising:

filtering an input and feedback signals with an analog loop filter;

quantizing a result of the filtering to provide quantized output values;

providing feedback proportional to a result of the quantizing as an input to the filtering;

converting a result of the quantizing to a serial bit stream, wherein a ratio of the bit rate of the serial bit stream to a quantization rate of the quantizing is greater than unity but less than a minimum number of bits required to represent a set of possible values for the feedback provided by the providing.

19. The method of claim 18, wherein the converting generates the serial bit stream to encode differences between sequential values of the result of the quantizing at the quantization rate.

20. The method of claim 18, wherein the result of the quantizing is constrained such that the converting encodes the result of the quantizing with a set of codes smaller than the number of codes available in the serial bit stream, whereby additional information is embedded in the serial bit stream by selecting among two or more redundant codes both representing a same next result of the quantizing, but different values of the additional information.

21. The method of claim 20, wherein the converting generates the serial bit stream to encode differences between sequential values of the result of the quantizing at the quantization rate, and wherein the serial bit stream encodes the additional information including an indication of an absolute level of the result of the quantizing encoded over multiple frames of the serial bit stream.

22. The method of claim 20, wherein the converting encodes the serial bit stream with the additional information including synchronization information indicating the position of frames of values of the result of the quantizing within the serial bit stream.

23. The method of claim 20, wherein the quantizing is a first quantizing and further comprising:

second filtering second input and second feedback signals with another analog loop filter;

second quantizing a result of the second filtering to provide second quantized output values; and

providing another feedback signal proportional to a result of the second quantizing to as an input to the second filtering, and wherein the converting further encodes a result of the second quantizing along with the result of the first quantizing, and wherein the converting further encodes the additional information including a framing indication for indicating whether a given value in the serial bit stream is one of the result of the first quantizing or the result of the second quantizing.

24. The method of claim 23, wherein the quantization rate is a first quantization rate of the first quantizing, and wherein values of the result of the second quantizing are generated at a second quantization rate that differs from the first quantization rate.

25. The method of claim 20, wherein the serial bit stream encodes a set of differences between sequential values of the result of the quantizing including only a single bit increment, a single bit decrement, and no change, and wherein the serial bit stream encodes a first set of codes for each of the elements of the set of differences and a second code representing a particular element of the set of differences in addition to the corresponding particular one of first codes that represents the particular element, and wherein the serial data circuit encodes the additional information in a pattern formed by generation of the particular one of the first codes and the second codes when the result of the quantizing is equal to the particular element of the set of differences.

26. The method of claim 18, wherein the serial bit stream is a two bit code generated at the quantization rate of the quantizing and representing three values of the result of the quantizing.

27. The method of claim 18, further comprising:

coupling the serial bit stream through a transformer through a first winding of the transformer; and

decoding the serial bit stream from a signal received from a second winding of the transformer to obtain the quantized output values.

28. The method of claim 27, further comprising receiving at least one of a power supply voltage for powering the analog-to-digital converter or a clock signal for operating the analog-to-digital converter from the first winding of the transformer.

29. The method of claim 18, further comprising integrating a result of said quantizing with a digital integrator, and wherein the providing provides the feedback from a result of the integrating.