Spatial modulator display system using two memories and display time slices having differing times

• US 7,903,104 B2
• Filed: 03/21/2007
• Issued: 03/08/2011
• Est. Priority Date: 03/21/2007
• Status: Active Grant

• Current Assignee: Spatial Photonics Incorporated (Himax Technologies Incorporated)
• Original Assignee: Spatial Photonics Incorporated (Himax Technologies Incorporated)
• Inventors: Chen, Chih-Liang, Sun, Alex Hung-Pin
• Primary Examiner(s): Mengistu; Amare
• Assistant Examiner(s): XAVIER, ANTONIO J
• Application Number:
  US11/689,464
• Publication Number:
  US 20080231568A1
• Time in Patent Office: 1,448 Days
• Field of Search: None
• US Class Current: 345/204
• CPC Class Codes: G09G 2300/0857 Static memory circuit, e.g. flip-flop
• CPC Class Codes: G09G 2310/0289 Details of voltage level shifters arranged for use in a driving circuit
• CPC Class Codes: G09G 2320/0252 Improving the response speed
• CPC Class Codes: G09G 3/2033 with splitting one or more sub-frames corresponding to the most significant bits into two or more sub-frames
• CPC Class Codes: G09G 3/346 based on modulation of the reflection angle, e.g. micromirrors micromirrors devices per se G02B26/0833

Abstract

A spatial light modulator having two static random access memory (SRAM) devices, including a display controller configured with a display sequence, the display sequence including a first display slice and a second display slice, the first display slice having a display time less than two times a minimum time period determined by the time of a write event, and the second display slice having a display time of more than two times the minimum time period. The controller controls write events from the two SRAM devices, and the first display slice and second display slice are ordered in the display sequence so that the controller causes the spatial light modulator to output light and causes the two SRAM devices each to perform a write event during the second display slice.

Claims

1. A spatial light modulator system, comprising:

an array of pixel cells each comprising;

two static random access memory (SRAM) devices each configured to store digital data and perform a write event that takes a minimum time period;

a spatial light modulator configured to output light in an on direction or an off direction according to the write event; and

a controller configured with a display sequence, the display sequence including a first display slice and a second display slice, the first display slice having a display time less than two times the minimum time period and the second display slice having a display time of more than two times the minimum time period, wherein the controller controls write events from the two SRAM devices, and the first display slice and second display slice are ordered in the display sequence so that the controller is configured to cause the spatial light modulator to output light and the two SRAM devices to each perform a write event during the second display slice.

2. The spatial light modulator system of claim 1, wherein the write event produces a first voltage signal in the range of about 1.3 to 2.3 volts.

3. The spatial light modulator system of claim 1, further comprising a level shifter configured to receive the write event from the SRAM devices.

4. The spatial light modulator system of claim 3, wherein the level shifter outputs a second voltage signal in the range of about 4 to 6 volts.

5. The spatial light modulator system of claim 4, wherein the spatial light modulator includes a micro mirror plate configured to receive a reset signal, and further includes one or more electrodes.

6. The spatial light modulator system of claim 5, wherein the one or more electrodes are configured to receive the second voltage signal from the level shifter, and the micro mirror plate is configured to tilt in response to a third voltage signal and the second voltage signal.

7. The spatial light modulator system of claim 6, wherein the third voltage signal is in the range of about 15 to 50 volts.

8. The spatial light modulator system of claim 7, wherein the third voltage signal is in the range of about 20 to 40 volts.

9. The spatial light modulator system of claim 1, further comprising a multiplexer configured to select one of the two SRAM devices in response to an external signal, wherein a selected SRAM of the two SRAM devices is configured to write data to a level shifter.

10. The spatial light modulator system of claim 9, wherein the level shifter is configured to receive a global reset signal and to reset the spatial light modulator to a predetermined position in response to the global reset signal.

11. The spatial light modulator system of claim 10, wherein the spatial light modulator includes a tiltable micro mirror plate supported by a substrate, wherein the micro mirror is configured to tilt to an on position to direct the light in the on direction or an off position to direct the light to the off direction in response to the global reset signal.

12. The spatial light modulator system of claim 9, wherein the level shifter comprises a plurality of MOSFET devices.

13. The spatial light modulator system of claim 12, wherein two of the plurality of MOSFET devices in the level shifter form a cross-coupled latch.

14. The spatial light modulator system of claim 1, wherein each of the at least two SRAM devices comprises a plurality of MOSFET devices.

15. The spatial light modulator system of claim 1, wherein the spatial light modulator includes a tiltable micro mirror plate supported by a substrate and one or more electrodes under the micro mirror plate.