Liquid crystal display and a defect correcting method for the same

• US 7,903,190 B2
• Filed: 07/30/2010
• Issued: 03/08/2011
• Est. Priority Date: 12/14/2004
• Status: Active Grant

• Current Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Enda, Kenji, Takeuchi, Masanori, Noda, Tomoki, Tsubata, Toshihide
• Primary Examiner(s): Ullah; Akm E
• Application Number:
  US12/847,092
• Publication Number:
  US 20100296020A1
• Time in Patent Office: 221 Days
• Field of Search: 349/54, 349/90, 349/38
• US Class Current: 349/54
• CPC Class Codes: G02F 1/1309 Repairing; Testing
• CPC Class Codes: G02F 1/134309 characterised by their geometrical arrangement
• CPC Class Codes: G02F 1/136263 Line defects
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: G02F 2201/508 Pseudo repairing, e.g. a defective part is brought into a condition in which it does not disturb the functioning of the device

Abstract

A liquid crystal display uses a pixel division method by which the size of a defect can be reduced much more than conventionally possible, and a defect correcting method for the liquid crystal display. The liquid crystal display is provided with an active matrix array substrate including a plurality of gate lines and a plurality of source lines arranged on a transparent substrate so as to intersect with each other, and a plurality of pixel electrodes arranged in a matrix, each pixel electrode including an assembly of a plurality of sub-pixel electrodes, separate TFTs respectively connected to the sub-pixel electrodes in the vicinity of an intersection portion of the gate line and the source line, the TFTs being driven by the common gate line and the common source line, and at least one opening portion being formed in a lower-layer side line placed in a lower layer at the intersection portion.

Claims

1. A liquid crystal display provided with an active matrix array substrate, the active matrix array substrate comprising:

a plurality of gate lines and a plurality of source lines arranged on a transparent substrate so as to intersect with each other; and

a plurality of pixel electrodes arranged in a matrix, each of the pixel electrodes including;

an assembly of a plurality of sub-pixel electrodes;

separate active elements respectively connected to the sub-pixel electrodes in the vicinity of an intersection portion of the gate line and the source line; and

at least one opening portion being formed in a lower-layer side line located in a lower layer at the intersection portion of the gate line and the source line.

2. The liquid crystal display according to claim 1, wherein the lower-layer side line is the gate line, and an upper-layer side line which is located in an upper layer of the lower-layer side line is the source line.

3. The liquid crystal display according to claim 1, further comprising an additional source line being partially connected to and extending along the source line.

4. The liquid crystal display according to claim 1, further comprising a bypass line being connected to the source line at the intersection portion.

5. The liquid crystal display according to claim 1, wherein the opening portion does not include at least one of an electrode layer and a semiconductor layer.

6. A defect correcting method for a liquid crystal display, comprising at least the steps of:

providing a liquid crystal display including an active matrix array substrate, the active matrix array substrate including a plurality of gate lines and a plurality of source lines arranged on a transparent substrate so as to intersect with each other, a plurality of pixel electrodes arranged in a matrix, each of the pixel electrodes including an assembly of a plurality of sub-pixel electrodes, separate active elements respectively connected to the sub-pixel electrodes in the vicinity of an intersection portion of the gate line and the source line, and at least one opening portion being formed in a lower-layer side line located in a lower layer at the intersection portion of the gate line and the source line;

cutting an upper-layer side line passing above the opening portion; and

cutting a line including a defective section in the cut line to isolate the defective section.