Resistance random access memory having common source line
First Claim
1. A resistance random access memory (RRAM) in which a write operation writing data having a first state and a second state to a selected memory cell is performed through first and second write paths formed in mutually opposite directions, the memory comprising:
- a plurality of word lines;
a plurality of bit lines;
a memory cell array having a plurality of memory cells which are disposed at the intersections of the word and bit lines to form a matrix of rows and columns and each have an access transistor and a resistive memory device, wherein the resistive memory device is formed of SrZrO3 disposed between a top electrode and a bottom electrode; and
a plurality of source lines each disposed between every two word lines and in the same direction as the word lines, and each connected to source terminals of corresponding access transistors having gate terminals connected to corresponding two word lines,wherein when the first state and the second state write operations are performed respectively, a selected source line voltage and a selected word line voltage are maintained equally, and the selected source line voltage during the first state and the second state write operations is a positive voltage.
1 Assignment
0 Petitions
Accused Products
Abstract
A resistance random access memory (RRAM) having a source line shared structure and an associated data access method. The RRAM, in which a write operation of writing data of first state and second state to a selected memory cell is performed through first and second write paths having mutually opposite directions, includes word lines, bit lines, a memory cell array and a plurality of source lines. The memory cell array includes a plurality of memory cells each constructed of an access transistor coupled to a resistive memory device. The memory cells are disposed in a matrix of rows and columns and located at each intersection of a word line and a bit line. Each of the plurality of source lines is disposed between a pair of word lines and in the same direction as the word lines. A positive voltage is applied to a source line in a memory cell write operation. Through the source line shared structure, occupied chip area is reduced and, in a write operating mode, a bit line potential can be determined within a positive voltage level range.
34 Citations
9 Claims
-
1. A resistance random access memory (RRAM) in which a write operation writing data having a first state and a second state to a selected memory cell is performed through first and second write paths formed in mutually opposite directions, the memory comprising:
-
a plurality of word lines; a plurality of bit lines; a memory cell array having a plurality of memory cells which are disposed at the intersections of the word and bit lines to form a matrix of rows and columns and each have an access transistor and a resistive memory device, wherein the resistive memory device is formed of SrZrO3 disposed between a top electrode and a bottom electrode; and a plurality of source lines each disposed between every two word lines and in the same direction as the word lines, and each connected to source terminals of corresponding access transistors having gate terminals connected to corresponding two word lines, wherein when the first state and the second state write operations are performed respectively, a selected source line voltage and a selected word line voltage are maintained equally, and the selected source line voltage during the first state and the second state write operations is a positive voltage. - View Dependent Claims (2, 3, 4, 5, 6, 7)
-
-
8. A resistance random access memory (RRAM) in which a write operation writing data having a first state and a second state to a selected memory cell is performed through first and second write paths formed in mutually opposite directions, the memory comprising:
-
a plurality of word lines; a plurality of bit lines; a memory cell array having a plurality of memory cells which are disposed at the intersections of the word and bit lines to form a matrix of rows and columns and each have an access transistor and a resistive memory device, wherein the resistive memory device is formed of a thin film of polycrystal material PrCaMnO3 disposed between a top electrode and a bottom electrode; and a plurality of source lines each disposed between every two word lines and in the same direction as the word lines, and each connected to source terminals of corresponding access transistors having gate terminals connected to corresponding two word lines, wherein when the first state and the second state write operations are performed respectively, a selected source line voltage and a selected word line voltage are maintained equally, and the selected source line voltage during the first state and the second state write operations is a positive voltage. - View Dependent Claims (9)
-
Specification