System, method, and computer program product for increasing a lifetime of a plurality of blocks of memory

• US 7,903,486 B2
• Filed: 11/19/2007
• Issued: 03/08/2011
• Est. Priority Date: 11/19/2007
• Status: Expired due to Fees

• Current Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Original Assignee: SandForce, Inc. (Broadcom, Inc.)
• Inventors: Danilak, Radoslav
• Primary Examiner(s): Le; Vu A
• Assistant Examiner(s): Yang; Han
• Application Number:
  US11/942,631
• Publication Number:
  US 20090129163A1
• Time in Patent Office: 1,205 Days
• Field of Search: 365/201, 365/185.24, 365/230.03
• US Class Current: 365/201
• CPC Class Codes: G06F 11/1072 in multilevel memories
• CPC Class Codes: G06F 12/023 Free address space management
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/1044 Space efficiency improvement
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 2212/7202 Allocation control and policies
• CPC Class Codes: G06F 2212/7205 Cleaning, compaction, garbage collection, erase control
• CPC Class Codes: G06F 2212/7211 Wear leveling
• CPC Class Codes: G06F 3/0608 Saving storage space on storage systems
• CPC Class Codes: G06F 3/0616 in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]
• CPC Class Codes: G06F 3/0631 by allocating resources to storage systems
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0649 Lifecycle management
• CPC Class Codes: G06F 3/0652 Erasing, e.g. deleting, data cleaning, moving of data to a wastebasket
• CPC Class Codes: G06F 3/0653 Monitoring storage devices or systems
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0673 Single storage device
• CPC Class Codes: G11C 14/009 and the nonvolatile element is a resistive RAM element, i.e. programmable resistors, e.g. formed of phase change or chalcogenide material
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: G11C 16/26 : Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/349 : Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: G11C 16/3495 : Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically
• CPC Class Codes: G11C 17/00 : Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
• CPC Class Codes: G11C 29/04 : Detection or location of defective memory elements , e.g. cell constructio details, timing of test signals
• CPC Class Codes: G11C 29/52 : Protection of memory contents; Detection of errors in memory contents

Abstract

A system, method, and computer program product are provided for increasing a lifetime of a plurality of blocks of memory. In operation, at least one factor that affects a lifetime of a plurality of blocks of memory is identified. Additionally, the plurality of blocks to write is selected, based on the at least one factor.

Claims

1. A method, comprising:

calculating a respective lifetime expectancy score for each of a plurality of blocks of a memory based at least in part on a respective count percentage of free space of each of the blocks;

determining an order to write and recycle the blocks, based at least in part on at least some of the respective lifetime expectancy scores; and

wherein a total amount of the blocks that are erased and written is minimized while lifetime expectancy score variation between the blocks is equalized.

2. The method of claim 1, wherein the calculating is further based at least in part on a respective number of errors during a respective read operation involving each of the blocks.

3. The method of claim 2, wherein the errors are detected errors.

4. The method of claim 2, wherein the errors are corrected errors.

5. The method of claim 1, wherein the calculating is further based at least in part on a respective duration between a respective program operation and a respective read operation involving each of the blocks.

6. The method of claim 1, wherein the calculating is further based at least in part on a respective number of times each of the blocks is respectively erased.

7. The method of claim 1, wherein the calculating is further based at least in part on a respective duration required to respectively erase each of the blocks.

8. The method of claim 1, wherein the calculating is further based at least in part on a respective duration required to respectively program each of the blocks.

9. The method of claim 1, wherein the calculating is further based at least in part on a respective number of retries required to respectively program each of the blocks.

10. The method of claim 1, wherein the calculating is further based at least in part on a respective number of intervening reads of a page associated with each of the blocks.

11. The method of claim 1, wherein the calculating is further based at least in part on a respective number of intervening reads in a neighboring page associated with each of the blocks.

12. The method of claim 1, wherein a first one of the blocks with a longer estimated lifetime is written before a second one of the blocks with a shorter estimated lifetime.

13. The method of claim 12, wherein the respective lifetime expectancy score for the second one of the blocks with the shorter estimated lifetime is above a threshold value established for lifetime expectancy scores.

14. The method of claim 13, wherein the respective lifetime expectancy score for the first one of the blocks with the longer estimated lifetime is below the threshold value established for lifetime expectancy scores.

15. The method of claim 1, wherein the memory includes a mechanical storage device.

16. The method of claim 1, wherein the memory includes a volatile memory device.

17. The method of claim 1, wherein the memory includes a nonvolatile memory device.

18. The method of claim 17, wherein the nonvolatile memory device includes at least one of a single-bit per cell NOR flash memory, a multi-bit per cell NOR flash memory, a single-bit per cell NAND flash memory, and a multi-bit per cell NAND flash memory.

19. The method of claim 1, further including storing a history of use of the blocks.

20. A tangible computer readable medium having a set of instructions stored therein which when executed by a processing element causes the processing element to perform functions comprising:

calculating a respective lifetime expectancy score for each of a plurality of blocks of a memory based at least in part on a respective count percentage of free space of each of the blocks;

determining an order to write and recycle the blocks, based at least in part on at least some of the respective lifetime expectancy scores; and

wherein a total amount of the blocks that are erased and written is minimized while lifetime expectancy score variation between the blocks is equalized.