Semiconductor memory device, and method of controlling the same

• US 7,903,487 B2
• Filed: 08/29/2008
• Issued: 03/08/2011
• Est. Priority Date: 11/09/1999
• Status: Expired due to Fees

• Current Assignee: Socionext Inc.
• Original Assignee: Fujitsu Semiconductor Limited (Fujitsu Limited)
• Inventors: Fujioka, Shinya, Sato, Kotoku, Nishimura, Koichi, Kawakubo, Tomohiro
• Primary Examiner(s): PHAN, TRONG Q
• Application Number:
  US12/201,922
• Publication Number:
  US 20090010080A1
• Time in Patent Office: 921 Days
• Field of Search: 365/203, 365/205, 365/207, 365/208, 365/222, 365/226, 365/227, 365/228, 365/229, 365/233.1, 327/108
• US Class Current: 365/203
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3234 Power saving characterised by the action undertaken
• CPC Class Codes: G06F 1/3268 Power saving in hard disk drive
• CPC Class Codes: G06F 1/3275 Power saving in memory, e.g. RAM, cache
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles
• CPC Class Codes: G11C 11/40615 Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs
• CPC Class Codes: G11C 14/00 Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
• CPC Class Codes: G11C 2207/2227 Standby or low power modes
• CPC Class Codes: G11C 2211/4067 Refresh in standby or low power modes
• CPC Class Codes: G11C 5/14 Power supply arrangements , e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
• CPC Class Codes: G11C 5/145 Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor G11C5/141 takes precedence
• CPC Class Codes: G11C 5/147 Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops G11C5/141 takes precedence
• CPC Class Codes: H02M 3/07 using capacitors charged and discharged alternately by semiconductor devices with control electrode , e.g. charge pumps
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02D 30/50 in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

An internal voltage generator when activated, generates an internal voltage to be supplied to an internal circuit. Operating the internal voltage generator consumes a predetermined amount of the power. In response to a control signal from the exterior, an entry circuit inactivates the internal voltage generator. When the internal voltage generator is inactivated, the internal voltage is not generated, thereby reducing the power consumption. By the control signal from the exterior, therefore, a chip can easily enter a low power consumption mode. The internal voltage generator is exemplified by a booster for generating the boost voltage of a word line connected with memory cells, a substrate voltage generator for generating a substrate voltage, or a precharging voltage generator for generating the precharging voltage of bit lines to be connected with the memory cells.

Claims

1. A semiconductor device comprising:

a memory core that includes a sense amplifier which receives an internal voltage from an internal power supply line, a precharging circuit and a dynamic memory cell;

a command decoder that receives a plurality of control signals and generates an internal command signal;

an internal voltage generator that generates the internal voltage based on an external voltage and supplies the internal voltage to the internal power supply line, the internal voltage generator including a precharging voltage generator that supplies a precharge voltage to a precharge voltage supply line coupled to the precharging circuit; and

an external voltage supplying circuit that supplies the external voltage to the internal power supply line,

wherein the precharging voltage generator stops supplying the precharge voltage to the precharge voltage supply line and the external voltage supplying circuit supplies the external voltage to the precharge voltage supply line during a low power consumption mode where a refresh operation is prohibited.

2. The semiconductor device according to claim 1, wherein a read operation or a write operation is executed in an operation mode, the read operation or the write operation is not executed in an idle mode and a self-refresh operation is executed in a self-refresh mode.

3. The semiconductor device according to claim 1, wherein the internal command signal indicates one of an operation mode where a read operation or a write operation is executed, an idle mode where the read operation or the write operation is not executed, a self-refresh mode where a self-refresh operation is executed and the low power consumption mode.

4. The semiconductor device according to claim 1, wherein the low power consumption mode is detected based on at least one of the plurality of control signals.

5. The semiconductor device according to claim 1, wherein the sense amplifier includes pair transistors coupled to the internal power supply line.

6. The semiconductor device according to claim 5, wherein the pair transistors are nMOS transistors, sources of which are coupled each other.

7. The semiconductor device according to claim 5, wherein the pair transistors are pMOS transistors, sources of which are coupled each other.

8. The semiconductor device according to claim 1, wherein the sense amplifier includes first pair transistors and second pair transistors and at least one of the first pair transistors and the second pair transistors are coupled to the internal power supply line.

9. The semiconductor device according to claim 1, wherein the semiconductor device operates in synchronized with a clock signal.

10. A semiconductor device comprising:

a memory core that includes a sense amplifier which receives an internal voltage from a internal power supply line, a precharging circuit and a dynamic memory cell;

a command decoder that receives a plurality of control signals and generates an internal command signal;

an internal voltage generator that generates the internal voltage based on an external voltage and supplies the internal voltage to the internal power supply line, the internal voltage generator including a precharging voltage generator that supplies a precharge voltage to a precharge voltage supply line coupled to the precharging circuit;

a low power entry circuit that receives at least one of the plurality of control signals and generates a low power signal indicating a low power consumption mode where a refresh operation is prohibited; and

an external voltage supplying circuit that supplies the external voltage to the internal power supply line,

wherein the precharging voltage generator stops supplying the precharge voltage to the precharge voltage supply line in response to the low power signal and the external voltage supplying circuit supplies the external voltage to the precharge voltage supply line during the low power consumption mode.

11. The semiconductor device according to claim 10, wherein a read operation or a write operation is executed in an operation mode, the read operation or the write operation is not executed in an idle mode, and a self-refresh operation is executed in a self-refresh mode.

12. The semiconductor device according to claim 10, wherein the command decoder decodes the plurality of control signals to generate the internal command signal indicating one of an idle mode, an operation mode and a self-refresh mode.

13. The semiconductor device according to claim 10, wherein the internal command signal indicates one of an operation mode where a read operation or a write operation is executed, an idle mode where the read operation or the write operation is not executed, and a self-refresh mode where a self-refresh operation is executed.

14. The semiconductor device according to claim 10, wherein the sense amplifier includes pair transistors coupled to the internal power supply line.

15. The semiconductor device according to claim 14, wherein the pair transistors are nMOS transistors, sources of which are coupled each other.

16. The semiconductor device according to claim 14, wherein the pair transistors are pMOS transistors, sources of which are coupled each other.

17. The semiconductor device according to claim 10, wherein the sense amplifier includes first pair transistors and second pair transistors and at least one of the first pair transistors and the second pair transistors are coupled to the internal power supply line.

18. The semiconductor device according to claim 10, wherein the semiconductor device operates in synchronized with a clock signal.

19. A semiconductor device comprising:

a memory core that includes a sense amplifier which receives an internal voltage from an internal power supply line, a precharging circuit and a dynamic memory cell;

an internal voltage generator that generates the internal voltage based on an external voltage and supplies the internal voltage to the internal power supply line, the internal voltage generator including a precharging voltage generator that supplies a precharge voltage to a precharge voltage supply line coupled to the precharging circuit; and

an external voltage supplying circuit that supplies the external voltage to the internal power supply line,

wherein the precharge voltage generator stops supplying the precharge voltage to the precharge voltage supply line and the external voltage supplying circuit supplies the external voltage to the precharge voltage supply line during a low power consumption mode where a refresh operation is prohibited.

20. The semiconductor device according to claim 19, wherein a read operation or a write operation is executed in an operation mode, the read operation or the write operation is not executed in an idle mode and a self-refresh operation is executed in a self-refresh mode.

21. The semiconductor device according to claim 19, wherein the low power consumption mode is detected based on an external control signal.

22. The semiconductor device according to claim 19, further comprising:

a low power entry circuit that generates a low power signal indicating the low power consumption mode base on an external control signal.

23. The semiconductor device according to claim 19, wherein the sense amplifier includes pair transistors coupled to the internal power supply line.

24. The semiconductor device according to claim 23, wherein the pair transistors are nMOS transistors, sources of which are coupled each other.

25. The semiconductor device according to claim 23, wherein the pair transistors are pMOS transistors, sources of which are coupled each other.

26. The semiconductor device according to claim 19, wherein the sense amplifier includes first pair transistors and second pair transistors and at least one of the first pair transistors and the second pair transistors are coupled to the internal power line.

27. The semiconductor device according to claim 19, wherein the semiconductor device operates in synchronized with a clock signal.

28. A semiconductor device comprising:

a memory core that includes a sense amplifier which received an internal voltage from an internal power supply line, a precharging circuit and a dynamic memory cell;

a command decoder that received a plurality of control signals and generates an internal command signal;

an internal voltage generator that generates the internal voltage based on an external voltage and supplies the internal voltage to the internal power supply line the internal voltage generator including a precharging voltage generator that supplies a precharge voltage to a precharge voltage supply line coupled to the precharging circuit; and

an external voltage supplying circuit that supplies the external voltage to the internal power supply line,

wherein the precharging voltage generator is inactivated and the external voltage supplying circuit supplies the external voltage to the precharge voltage supply line during a low power consumption mode.

29. The semiconductor device according to claim 28, wherein a read operation or a write operation is executed in an operation mode, the read operation or the write operation is not executed in an idle mode and a self-refresh operation is executed in a self-refresh mode.

30. The semiconductor device according to claim 28, wherein the internal command signal indicates one of an operation mode where a read operation or a write operation is executed, an idle mode where the read operation or the write operation is not executed, a self-refresh mode where a self-refresh operation is executed and the low power consumption mode.

31. The semiconductor device according to claim 28, wherein the low power consumption mode is detected based on at least one of the plurality of control signals.

32. The semiconductor device according to claim 28, wherein the sense amplifier includes pair transistors coupled to the internal power supply line.

33. The semiconductor device according to claim 32, wherein the pair transistors are nMOS transistors, sources of which are coupled each other.

34. The semiconductor device according to claim 32, wherein the pair transistors are PMOS transistors, sources of which are coupled each other.

35. The semiconductor device according to claim 28, wherein the sense amplifier includes first pair transistors and second pair transistors and at least one of the first pair transistors and the second pair transistors are coupled to the internal power supply line.

36. The semiconductor device according to claim 28 further comprising:

a low power entry circuit that generates a low power signal indicating the low power consumption mode base on an external control signal.

37. The semiconductor device according to claim 28, wherein the semiconductor device operates in synchronized with a clock signal.

38. A semiconductor device comprising:

a memory core that includes a sense amplifier which receives an internal voltage from an internal power supply line, a precharging circuit and a dynamic memory cell;

a command decoder that receives a plurality of control signals and generates an internal command signal;

an precharging voltage generator that includes a plurality of generator circuits and generates a precharge voltage based on an external voltage and supplies the precharge voltage to a precharge voltage supply line coupled to the precharging circuit; and

an external voltage supplying circuit that supplies the external voltage to the internal power supply line,

wherein at least one of generator circuits is inactivated and the external voltage supplying circuit supplies the external voltage to the precharge voltage supply line during a low power consumption mode where a refresh operation is prohibited.

39. The semiconductor device according to claim 38, wherein a read operation or a write operation is executed in an operation mode, the read operation or the write operation is not executed in an idle mode and a self-refresh operation is executed in a self-refresh mode.

40. The semiconductor device according to claim 38, wherein the internal command signal indicates one of an operation mode where a read operation or a write operation is executed, an idle mode where the read operation or the write operation is not executed, a self-refresh mode where a self-refresh operation is executed and the low consumption mode.

41. The semiconductor device according to claim 38, wherein the low power consumption mode is detected based on at least one of the plurality of control signals.

42. The semiconductor device according to claim 38, wherein the sense amplifier includes pair transistors coupled to the internal power supply line.

43. The semiconductor device according to claim 42, wherein the pair transistors are nMOS transistors, sources of which are coupled each other.

44. The semiconductor device according to claim 42, wherein the pair transistors are pMOS transistors, sources of which are coupled each other.

45. The semiconductor device according to claim 38, wherein the sense amplifier includes first pair transistors and second pair transistors and at least one of the first pair transistors and the second pair transistors are coupled to the internal power supply line.

46. The semiconductor device according to claim 38, further comprising:

a low power entry circuit that generates a low power signal indicating the low power consumption mode base on an external control signal.

47. The semiconductor device according to claim 38, wherein the semiconductor device operates in synchronized with a clock signal.

48. A semiconductor device comprising:

a memory core that operates with a first internal voltage in an operation mode and includes a sense amplifier which receives the first internal voltage from an internal power supply line, a precharging circuit and a dynamic memory cell;

a command decoder that receives a plurality of control signals and generates an internal command signal; and

a precharging voltage generator that generates a precharge voltage based on an external voltage and supplies the precharge voltage to a precharge voltage supply line coupled to the precharging circuit;

wherein the sense amplifier includes pair transistors, sources of which are coupled to the internal power supply line,

wherein the internal power supply line is supplied a second internal voltage, which is lower than the first internal voltage, in a low power consumption mode where a refresh operation is prohibited, and is supplied the first internal voltage in the operation mode, and

wherein the precharging voltage generator stops supplying the precharge voltage to the precharge voltage supply line and the external voltage supplying circuit supplies the external voltage to the precharge voltage supply line during the low power consumption mode.

49. The semiconductor device according to claim 48, further comprising:

an external voltage supplying circuit that supplies the second internal voltage to the internal power supply line in the low power consumption mode.

50. The semiconductor device according to claim 48, further comprising:

an internal voltage generator generates the first internal voltage,

wherein the internal voltage generator includes a plurality of circuits and at least one of the plurality of circuits stops in the low power consumption mode.

51. The semiconductor device according to claim 48, further comprising:

an internal voltage generator generates the first internal voltage,

wherein the internal voltage generator includes a plurality of circuits and at least one of the plurality of circuits stops when receiving a low power signal indicating the low power consumption mode.

52. The semiconductor device according to claim 48, wherein a read operation or a write operation is executed in an operation mode, the read operation or the write operation is not executed in an idle mode and a self-refresh operation is executed in a self-refresh mode.

53. The semiconductor device according to claim 48, wherein the internal command signal indicates one of an operation mode where a read operation or a write operation is executed, an idle mode where the read operation or the write operation is not executed, a self-refresh mode where a self-refresh operation is executed and the low consumption mode.

54. The semiconductor device according to claim 48, wherein the low power consumption mode is detected based on at least one of the plurality of control signals.

55. The semiconductor device according to claim 48, wherein the pair transistors are nMOS transistors, sources of which are coupled each other.

56. The semiconductor device according to claim 48, further comprising:

a second pMOS pair transistors, sources of which are coupled to the internal power supply line.

57. The semiconductor device according to claim 48, further comprising:

a low power entry circuit that generates a low power signal indicating the low power consumption mode base on an external control signal.

58. The semiconductor device according to claim 48, wherein the semiconductor device operates in synchronized with a clock signal.