Methods and arrangement for utilization rate display
First Claim
1. A network system comprising:
- a bus,a set of network ports,said set of network ports including a set of input network ports for receiving data traffic and a set of output network ports for outputting said data traffic,said set of input network ports including at least a first port;
logic arrangement for analyzing said data traffic andfor displaying said statistical data pertaining to said data traffic,said logic arrangement including at least a first counter and a second counter,said first counter and said second counter being associated with said first port,said logic arrangement being configured to increment said first counter for each occurrence of a valid data packet at said first port,said logic arrangement being further configured to increment said second counter for each byte of data received at said first port;
wherein said logic arrangement includes a field-programmable field array (FPGA),said FPGA is configured to perform analysis of said RX_DV signal and said RX_CLK signal to determine a utilization rate of a network device;
wherein said FPGA increases said first counter by one when said RX_DV rising edge is received, said RX_DV rising edge indicating a first valid data packet is being received by said first port;
wherein said FPGA increases said second counter when at least said RX_CLK falling edge is receivedwherein said bus is a reduced gigabit media independent interface (RGMII),said bus being configured to direct a copy of said data traffic to a set of monitoring devices,said data traffic including a plurality of control signals;
wherein at least a portion of said plurality of control signals includes an RX_DV signal,said RX_DV signal including an RX_DV rising edge and an RX_DV falling edge; and
a visual display arrangement, said visual display arrangement being configured to display statistical data pertaining to said data traffic.
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Accused Products
Abstract
An arrangement in a network device for displaying statistical data pertaining to data traffic that traverses the network device is provided. The arrangement includes a power supply arrangement for providing power to circuitry of the network device. The arrangement also includes a set of network ports, which includes a set of input network ports for receiving the data traffic and a set of output network ports for outputting the data traffic from the network device. The arrangement further includes logic arrangement for analyzing data traffic and for displaying statistical data pertaining to the data traffic. The arrangement yet also includes a visual display arrangement, which is configured to display the statistical data, whereas the data traffic is configured to traverse the network device between the set of input network ports and the set of output network ports irrespective whether power is provided to the circuitry of the network device.
65 Citations
15 Claims
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1. A network system comprising:
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a bus, a set of network ports, said set of network ports including a set of input network ports for receiving data traffic and a set of output network ports for outputting said data traffic, said set of input network ports including at least a first port; logic arrangement for analyzing said data traffic and for displaying said statistical data pertaining to said data traffic, said logic arrangement including at least a first counter and a second counter, said first counter and said second counter being associated with said first port, said logic arrangement being configured to increment said first counter for each occurrence of a valid data packet at said first port, said logic arrangement being further configured to increment said second counter for each byte of data received at said first port; wherein said logic arrangement includes a field-programmable field array (FPGA), said FPGA is configured to perform analysis of said RX_DV signal and said RX_CLK signal to determine a utilization rate of a network device; wherein said FPGA increases said first counter by one when said RX_DV rising edge is received, said RX_DV rising edge indicating a first valid data packet is being received by said first port; wherein said FPGA increases said second counter when at least said RX_CLK falling edge is received wherein said bus is a reduced gigabit media independent interface (RGMII), said bus being configured to direct a copy of said data traffic to a set of monitoring devices, said data traffic including a plurality of control signals; wherein at least a portion of said plurality of control signals includes an RX_DV signal, said RX_DV signal including an RX_DV rising edge and an RX_DV falling edge; and a visual display arrangement, said visual display arrangement being configured to display statistical data pertaining to said data traffic. - View Dependent Claims (2, 3, 4, 5, 6)
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7. a method for enabling statistical data pertaining to data traffic that traverses a network device between a set of input network ports and a set of output network ports to be viewed on a visual display arrangement, said input network ports including at least a first port, said method comprising:
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associating said first port with a first counter and a second counter; extracting an RX_DV signal and an RX_CLK signal from a bus, wherein said RX_CLK signal includes an RX_CLK rising edge and an RX_CLK falling edge, said RX_CLK rising edge being a first byte of data and said RX_CLK falling edge being a second byte of data; said bus being coupled with said first port; associating said first counter with said RX_DV signal; associating said second counter with said RX_CLK signal; incrementing said first counter for each occurrence of a valid data packet at said first port, said occurrence of a valid data packet being indicated by said RX_DV signal; incrementing said second counter for each byte of data received at said first port, said byte of date received at said first port being indicated by said RX_CLK signal; analyzing at least said first counter and said second counter to generate said statistical data; performing said analyzing using a logic arrangement, wherein said logic arrangement includes a field-programmable field array (FPGA), said FPGA configured to perform analysis of said RX_DV signal and said RX_CLK signal to determine a utilization rate of said network device; and displaying said statistical data on said visual display arrangement. - View Dependent Claims (8, 9, 10, 11, 12, 13, 14, 15)
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Specification