Power supply filtering for programmable logic device having heterogeneous serial interface architecture

• US 7,903,679 B1
• Filed: 01/11/2007
• Issued: 03/08/2011
• Est. Priority Date: 04/11/2006
• Status: Active Grant

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Tran, Thungoc M., Wong, Wilson, Shumarayev, Sergey, Hoang, Tim Tri
• Primary Examiner(s): Vu; Thong H
• Application Number:
  US11/622,396
• Time in Patent Office: 1,517 Days
• Field of Search: 370/419, 370/474, 370/328, 370/488, 370/286, 370/526, 370/362, 455/165, 455/188, 455/41
• US Class Current: 370/419
• CPC Class Codes: H03K 19/17744 for input/output signals

Abstract

In a programmable logic device with a number of different types of serial interfaces, different power supply filtering schemes are applied to different interfaces. For interfaces operating at the lowest data rates—e.g., 1 Gbps—circuit-board level filtering including one or more decoupling capacitors may be provided. For interfaces operating at somewhat higher data rates—e.g., 3 Gbps—modest on-package filtering also may be provided, which may include power-island decoupling. For interfaces operating at still higher data rates—e.g., 6 Gbps—more substantial on-package filtering, including one or more on-package decoupling capacitors, also may be provided. For interfaces operating at the highest data rates—e.g., 10 Gbps—on-die filtering, which may include one or more on-die filtering or regulating networks, may be provided. The on-die regulators may be programmably bypassable allowing a user to trade off performance for power savings.

Claims

1. Filter circuitry for a serial interface in a programmable logic device, said programmable logic device being fabricated on a die which is packaged in a package, said filter circuitry comprising at least one of:

die-level filtering circuitry for filtering a first range of frequencies; and

package-level filtering circuitry for filtering a second range of frequencies lower than said first range of frequencies.

2. The filter circuitry of claim 1 wherein at least one of said die-level filtering circuitry and said package-level filtering circuitry comprises a reactance.

3. The filter circuitry of claim 2 wherein said reactance comprises a capacitor.

4. The filter circuitry of claim 1 wherein said package-level filtering circuitry comprises selective routing of power relative to ground.

5. The filter circuitry of claim 1 wherein said die-level filtering circuitry further comprises one of (a) a respective filter network, and (b) a respective regulator circuit, each said respective filter network and respective regulator being matched to a respective portion of said serial interface.

6. The filter circuitry of claim 5 wherein said die-level filtering circuitry further comprises a respective selectable bypass for each said respective filter network and respective regulator.

7. The filter circuitry of claim 1 wherein, when said package is mounted on a circuit board, said filter circuitry for said serial interface further comprises at least one of:

said die-level filtering circuitry;

said package-level filtering circuitry; and

board-level filtering circuitry for filtering a third range of frequencies lower than said second range of frequencies.

8. The filter circuitry of claim 7 wherein said board-level filtering circuitry comprises a reactance.

9. The filter circuitry of claim 8 wherein said reactance comprises a capacitor.

10. The filter circuitry of claim 8 wherein said reactance comprises an inductor.

11. The filter circuitry of claim 7 wherein:

said serial interface operates at a data rate up to about 1 Gbps; and

said filter circuitry comprises said board-level filter circuitry.

12. The filter circuitry of claim 11 wherein:

said filter circuitry further comprises said package-level filter circuitry; and

said package-level filter circuitry comprises selective routing of power relative to ground.

13. The filter circuitry of claim 7 wherein:

said serial interface operates at a data rate up to about 3 Gbps; and

said filter circuitry comprises said board-level filter circuitry and said package-level filter circuitry.

14. The filter circuitry of claim 13 wherein:

said serial interface comprises a voltage-controlled oscillator; and

said filter circuitry further comprises said die-level filter circuitry to filter said voltage-controlled oscillator.

15. The filter circuitry of claim 7 wherein:

said serial interface operates at a data rate up to about 6 Gbps; and

said filter circuitry comprises said board-level filter circuitry, said package-level filter circuitry, and said die-level filter circuitry.

16. The filter circuitry of claim 15 wherein:

said serial interface comprises a voltage-controlled oscillator, a loop filter, and a charge pump; and

said filter circuitry further comprises said die-level filter circuitry to filter at least one of said voltage-controlled oscillator, said loop filter, and said charge pump.

17. The filter circuitry of claim 16 wherein said die-level filter circuitry comprises one of (a) a respective filter network, and (b) a respective regulator circuit, each said respective filter network and respective regulator being matched to one of said voltage-controlled oscillator, said loop filter, and said charge pump.

18. The filter circuitry of claim 17 wherein said die-level filtering circuitry further comprises a respective selectable bypass for each said respective filter network and respective regulator.

19. The filter circuitry of claim 7 wherein:

said serial interface operates at a data rate up to about 10 Gbps; and

said filter circuitry comprises said board-level filter circuitry, said package-level filter circuitry, and said die-level filter circuitry.

20. The filter circuitry of claim 19 wherein:

said serial interface comprises a voltage-controlled oscillator, a loop filter, and a charge pump; and

said filter circuitry further comprises said die-level filter circuitry to filter said voltage-controlled oscillator, said loop filter, and said charge pump.

21. The filter circuitry of claim 20 wherein said die-level filter circuitry comprises one of (a) a respective filter network, and (b) a respective regulator circuit, each said respective filter network and respective regulator being matched to one of said voltage-controlled oscillator, said loop filter, and said charge pump.

22. The filter circuitry of claim 21 wherein said die-level filtering circuitry further comprises a respective selectable bypass for each said respective filter network and respective regulator.

23. The filter circuitry of claim 20 wherein said die-level filter circuitry further comprises a reactance.

24. The filter circuitry of claim 23 wherein said reactance comprises a capacitance.

25. A system including a programmable logic device fabricated on a die which is packaged in a package, said package being mounted on a circuit board with additional functional circuitry, said programmable logic device including at least one serial interface and filter circuitry for filtering said serial interface, said filter circuitry comprising, for each said serial interface, at least one of:

die-level filtering circuitry for filtering a first range of frequencies;

package-level filtering circuitry for filtering a second range of frequencies lower than said first range of frequencies; and

board-level filtering circuitry for filtering a third range of frequencies lower than said second range of frequencies.

26. The system of claim 25 wherein at least one of said die-level filtering circuitry, said package-level filtering circuitry, and said board-level filtering circuitry, comprises a reactance.

27. The system of claim 26 wherein said reactance comprises a capacitor.

28. The system of claim 26 wherein said board-level filtering circuitry comprises an inductor.

29. The system of claim 25 wherein said package-level filtering circuitry comprises selective routing of power relative to ground.

30. The system of claim 25 wherein said die-level filtering circuitry further comprises one of (a) a respective filter network, and (b) a respective regulator circuit, each said respective filter network and respective regulator being matched to a respective portion of said serial interface.

31. The system of claim 30 wherein said die-level filtering circuitry further comprises a respective selectable bypass for each said respective filter network and respective regulator.