Asynchronous computer communication
First Claim
1. A computer array, comprising:
- a plurality of computers; and
a plurality of bidirectional data paths connecting the computers, each of said data paths dedicated between a pair of the computers and including a read line, a write line, and a plurality of data lines; and
whereineach of said computers includes its own sequencer, said sequencer responsive to input from at least one of an instruction word and an acknowledgement signal and operative to produce a timing pulse for causing the execution of instructions by said computer associated with said sequencer;
when a first one of said computers attempts a communication with a second one of said computers then said first one of said computers stops operation by suspending the triggering of a timing pulse from said sequencer of said first one of said computers until said second one of said computers is ready to complete said communication;
said first one of said computers indicates its readiness to communicate with said second one of said computers by asserting a first signal on one of said read line and said write line connecting said first one of said computers and said second one of said computers;
said second one of said computers indicates its readiness to communicate with said first one of said computers by asserting a second signal on the other of said read line and said write line connecting said first one of said computers and said second one of said computers;
when said first one of said computers and said second one of said computers have indicated their readiness to communicate, then data is transferred between said first one of said computers and said second one of said computers via said data lines connecting said first one of said computers and said second one of said computers;
when said data is transferred between said first one of said computers and said second one of said computers, then said first signal and said second signal change;
when said first signal and said second signal change, then said first one of said computers resumes operation;
said sequencer is suspended from triggering a timing pulse responsive to a processing unit of said first one of said computers executing at least one of a read instruction and a write instruction;
said sequencer is triggered to produce a timing pulse responsive to said processing unit of said first one of said computers executing an instruction other than said read instruction and said write instruction;
said computers communicate with one another in an asynchronous manner; and
said plurality of computers is integrated on a single die.
5 Assignments
0 Petitions
Accused Products
Abstract
A computer array (10) has a plurality of computers (12). The computers (12) communicate with each other asynchronously, and the computers (12) themselves operate in a generally asynchronous manner internally. When one computer (12) attempts to communicate with another it goes to sleep until the other computer (12) is ready to complete the transaction, thereby saving power and reducing heat production. A plurality of read lines (18), write lines (20) and data lines (22) interconnect the computers (12). When one computer (12) sets a read line (18) high and the other computer sets a corresponding write line (20) then data is transferred on the data lines (22). When both the read line (18) and corresponding write line (20) go low this allows both communicating computers (12) to know that the communication is completed. An acknowledge line (72) goes high to restart the computers (12).
197 Citations
32 Claims
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1. A computer array, comprising:
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a plurality of computers; and a plurality of bidirectional data paths connecting the computers, each of said data paths dedicated between a pair of the computers and including a read line, a write line, and a plurality of data lines; and
whereineach of said computers includes its own sequencer, said sequencer responsive to input from at least one of an instruction word and an acknowledgement signal and operative to produce a timing pulse for causing the execution of instructions by said computer associated with said sequencer; when a first one of said computers attempts a communication with a second one of said computers then said first one of said computers stops operation by suspending the triggering of a timing pulse from said sequencer of said first one of said computers until said second one of said computers is ready to complete said communication; said first one of said computers indicates its readiness to communicate with said second one of said computers by asserting a first signal on one of said read line and said write line connecting said first one of said computers and said second one of said computers; said second one of said computers indicates its readiness to communicate with said first one of said computers by asserting a second signal on the other of said read line and said write line connecting said first one of said computers and said second one of said computers; when said first one of said computers and said second one of said computers have indicated their readiness to communicate, then data is transferred between said first one of said computers and said second one of said computers via said data lines connecting said first one of said computers and said second one of said computers; when said data is transferred between said first one of said computers and said second one of said computers, then said first signal and said second signal change; when said first signal and said second signal change, then said first one of said computers resumes operation; said sequencer is suspended from triggering a timing pulse responsive to a processing unit of said first one of said computers executing at least one of a read instruction and a write instruction; said sequencer is triggered to produce a timing pulse responsive to said processing unit of said first one of said computers executing an instruction other than said read instruction and said write instruction; said computers communicate with one another in an asynchronous manner; and said plurality of computers is integrated on a single die. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 24, 25, 26, 27, 28, 29, 30, 31, 32)
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9. A method for communicating between a first computer device and a second computer device, the first computer device being connected to the second computer device by a data path including a read line, a write line, and a plurality of data lines, the method comprising:
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causing the first computer device to indicate its readiness to communicate with the second computer device by asserting a first signal on one of the read line and the write line connecting the first computer device and the second computer device; causing the first computer device to stop operation after indicating its readiness to communicate with the second computer device; causing the second computer device to indicate its readiness to complete the communication by asserting a second signal on the other of the read line and the write line connecting the first computer device and the second computer device; transferring data between the first computer device and the second computer device via the plurality of data lines when the first computer device and the second computer device have indicated their readiness to communicate; and causing at least one of the first computer device and the second computer device to acknowledge to the other of the first computer device and the second computer device that the communication is completed by changing the values of the first signal and the second signal; and causing the first computer device to resume operation when the values of the first signal and the second signal change; and
wherein the first computer device indicates its readiness to read or write to the second computer device;the first computer device includes a sequencer, the sequencer being responsive to input from at least one of an instruction word and the acknowledgement and operative to produce a timing pulse; the step of causing the first computer device to resume operation includes causing the first computer device to execute an instruction in response to the timing pulse; the first computer device and the second computer device communicate with one another in an asynchronous manner; and the first computer device and the second computer device are integrated on a single die. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16)
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17. A method for communicating between a pair of computers interconnected by a bidirectional data path including a read line, a write line, and a plurality of data lines, said method comprising:
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(a) causing a first computer to indicate its readiness to communicate by asserting a first signal on one of said read line and said write line; (b) causing said first computer to then cease operation after asserting said first signal; (c) causing a second computer to indicate its readiness to communicate to said first computer by asserting a second signal on the other of said read line and said write line; (d) transferring data between said first computer and said second computer via said plurality of data lines after said first signal and said second signal are asserted; and (e) causing said first computer to resume operation by detecting that said data has been transferred between said first computer and said second computer, said first computer detecting that said data has been transferred by detecting that the values of said first signal and said second signal have changed; and
whereinsaid first computer includes a sequencer, the sequencer being responsive to input from at least one of an instruction word and an acknowledgement signal and operative to produce a series of timing pulses for causing the execution of instructions; said step of causing said first computer to cease operation includes suspending the triggering of said sequencer such that said sequencer does not generate said timing pulse; said step of causing said first computer to resume operation includes triggering said sequencer such that said sequencer generates said timing pulse; said first computer and said second computer communicate with one another in an asynchronous manner; and said first computer and said second computer are integrated on a single die. - View Dependent Claims (18, 19, 20, 21, 22)
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23. A computer, comprising:
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means for communicating between a first computer and a second computer, said means including a read line, a write line, and a plurality of data lines; means for causing said first computer to indicate that it is ready to communicate by asserting a first signal on one of said read line and said write line; means for stopping said first computer until said second computer indicates that it is ready to communicate; means for causing said second computer to indicate that it is ready to communicate by asserting a second signal on the other of said read line and said write line; means for transferring a communication between said first computer and said second computer when said first computer and said second computer have indicated their readiness to communicate; means for acknowledging that said communication has been accomplished by changing the values of said first signal and said second signal; and
whereinsaid means for stopping said first computer stops said first computer until said means for acknowledging acknowledges that said communication has been accomplished; said means for stopping said first computer suspends the triggering of a timing pulse responsive to a processing unit of said first computer executing at least one of a read instruction and a write instruction; said means for stopping said first computer causes a timing pulse to be generated responsive to said processing unit of said first computer executing an instruction other than said read instruction and said write instruction; said first computer and said second computer communicate with one another in an asynchronous manner; and said first computer and said second computer are integrated on a single die.
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Specification