System and method for accessing interleaved data in a memory device
First Claim
1. A system for accessing data in a memory device comprising a plurality of memory units, the system comprising:
- a first interface configured to receive a plurality of data units and a corresponding plurality of non-sequential logical addresses; and
a management module coupled to the first interface and configured to map the plurality of non-sequential logical addresses to a plurality of sequential virtual addresses according to the order in which the data units in the plurality of data units are received by the first interface, the management module further configured to map the plurality of sequential virtual addresses to a corresponding plurality of physical addresses; and
a second interface coupled to the management module and configured to write the plurality of data units to the plurality of physical addresses in one write operation.
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Accused Products
Abstract
A memory and storage device includes a data management system for transferring data units referenced by logical addresses. The data management system maps the logical addresses to sequential virtual addresses according to the order the data units are received. The data management system also maps the sequential virtual addresses to sequential physical addresses in a memory block of a memory device. Additionally, the data management system can modify a data unit in the memory block by copying any other valid data units in the memory block to another memory block and writing the modified data unit into this other memory block. The data management system writes the valid data units and the modified data unit into sequential physical addresses of this other memory block.
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Citations
18 Claims
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1. A system for accessing data in a memory device comprising a plurality of memory units, the system comprising:
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a first interface configured to receive a plurality of data units and a corresponding plurality of non-sequential logical addresses; and a management module coupled to the first interface and configured to map the plurality of non-sequential logical addresses to a plurality of sequential virtual addresses according to the order in which the data units in the plurality of data units are received by the first interface, the management module further configured to map the plurality of sequential virtual addresses to a corresponding plurality of physical addresses; and a second interface coupled to the management module and configured to write the plurality of data units to the plurality of physical addresses in one write operation. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A system for accessing data in a memory device comprising a plurality of memory units, the system comprising:
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an input buffer configured to receive a plurality of data units and a corresponding plurality of non-sequential logical addresses; and a controller coupled to the input buffer and configured to map the plurality of non-sequential logical addresses to a plurality of sequential virtual addresses according to the order in which the data units in the plurality of data units are received in the input buffer, the controller further configured to map the plurality of sequential virtual addresses to a corresponding plurality of physical addresses and to issue a block write operation for writing the plurality of data units to the plurality of physical addresses. - View Dependent Claims (11, 12, 13, 14, 15)
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16. A method for accessing data in a memory device comprising a plurality of memory blocks, the method comprising:
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receiving a first plurality of data units and a corresponding first plurality of logical addresses; receiving a second plurality of data units and a corresponding second plurality of logical addresses, wherein the first and second pluralities of logical addresses are non-sequential; mapping the first plurality of logical addresses to a first plurality of sequential virtual addresses; mapping the second plurality of logical addresses to a second plurality of sequential virtual addresses; writing the first plurality of data units into a data buffer based on the first plurality of sequential virtual addresses; writing the second plurality of data units into the data buffer based on the second plurality of sequential virtual addresses, wherein the first and second plurality of data units are written into sequential memory addresses of the data buffer; mapping the first plurality of virtual addresses and the second plurality of virtual addresses to a plurality of physical addresses; and writing the first and second plurality of data units in the data buffer into the memory block at the plurality of physical addresses in one write operation. - View Dependent Claims (17, 18)
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Specification