System and method for accessing interleaved data in a memory device

• US 7,904,636 B2
• Filed: 02/21/2006
• Issued: 03/08/2011
• Est. Priority Date: 01/11/2002
• Status: Active Grant

• Current Assignee: Western Digital Technologies Incorporated (Western Digital Corporation)
• Original Assignee: STEC Incorporated (Western Digital Corporation)
• Inventors: Wu, Chien-Hung
• Primary Examiner(s): Thomas; Shane M
• Application Number:
  US11/358,673
• Publication Number:
  US 20060143426A1
• Time in Patent Office: 1,841 Days
• Field of Search: 711/103, 711/157, 711/203
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 3/0616 in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]

Abstract

A memory and storage device includes a data management system for transferring data units referenced by logical addresses. The data management system maps the logical addresses to sequential virtual addresses according to the order the data units are received. The data management system also maps the sequential virtual addresses to sequential physical addresses in a memory block of a memory device. Additionally, the data management system can modify a data unit in the memory block by copying any other valid data units in the memory block to another memory block and writing the modified data unit into this other memory block. The data management system writes the valid data units and the modified data unit into sequential physical addresses of this other memory block.

Claims

1. A system for accessing data in a memory device comprising a plurality of memory units, the system comprising:

a first interface configured to receive a plurality of data units and a corresponding plurality of non-sequential logical addresses; and

a management module coupled to the first interface and configured to map the plurality of non-sequential logical addresses to a plurality of sequential virtual addresses according to the order in which the data units in the plurality of data units are received by the first interface, the management module further configured to map the plurality of sequential virtual addresses to a corresponding plurality of physical addresses; and

a second interface coupled to the management module and configured to write the plurality of data units to the plurality of physical addresses in one write operation.

2. The system of claim 1, wherein the management module comprises a first data structure containing the mapping of the plurality of non-sequential logical addresses to the plurality of sequential virtual addresses.

3. The system of claim 2, wherein the first data structure comprises a data table.

4. The system of claim 2, wherein the management module comprises a second data structure containing the mapping of a plurality of virtual units to a plurality of physical units, each of the virtual units in the plurality of virtual units comprising a plurality of virtual addresses, each of the physical units in the plurality of physical units comprising a plurality of physical addresses of a memory block in the memory device.

5. The system of claim 4, wherein the second data structure comprises a data table.

6. The system of claim 5, wherein the data table comprises a plurality of table entries, each table entry comprising a mapped physical unit status indicator, a pointer indicating a number of available physical sectors and a mapped physical unit number.

7. The system of claim 1, wherein each data unit in the plurality of data units is a sector of data.

8. The system of claim 1, wherein each data unit in the plurality of data units is a page of data.

9. The system of claim 1, wherein the management module is further configured to perform a block write operation to write the plurality of data units into the plurality of memory blocks at the plurality of physical addresses.

10. A system for accessing data in a memory device comprising a plurality of memory units, the system comprising:

an input buffer configured to receive a plurality of data units and a corresponding plurality of non-sequential logical addresses; and

a controller coupled to the input buffer and configured to map the plurality of non-sequential logical addresses to a plurality of sequential virtual addresses according to the order in which the data units in the plurality of data units are received in the input buffer, the controller further configured to map the plurality of sequential virtual addresses to a corresponding plurality of physical addresses and to issue a block write operation for writing the plurality of data units to the plurality of physical addresses.

11. The system of claim 10, further comprising a memory coupled to the controller and configured to store a first table for mapping the plurality of non-sequential logical addresses to the plurality of sequential virtual addresses, wherein the controller is further configured to map the non-sequential logical addresses to the plurality of sequential virtual address based on the first table.

12. The system of claim 11, wherein the memory is further configured to store a second table for mapping a plurality of virtual units to a plurality of physical units, each of the virtual units in the plurality of virtual units comprising a plurality of virtual addresses, each of the physical units in the plurality of physical units comprising a plurality of physical addresses of a memory block in the memory device, wherein the controller is further configured to map the plurality of virtual units to the plurality of physical units based on the second table.

13. The system of claim 12, wherein the second table comprises a data table comprising a plurality of table entries, each table entry comprising a mapped physical unit status indicator, a pointer indicating a number of available physical sectors and a mapped physical unit number.

14. The system of claim 10, wherein each data unit in the plurality of data units is a sector of data.

15. The system of claim 10, wherein each data unit in the plurality of data units is a page of data.

16. A method for accessing data in a memory device comprising a plurality of memory blocks, the method comprising:

receiving a first plurality of data units and a corresponding first plurality of logical addresses;

receiving a second plurality of data units and a corresponding second plurality of logical addresses, wherein the first and second pluralities of logical addresses are non-sequential;

mapping the first plurality of logical addresses to a first plurality of sequential virtual addresses;

mapping the second plurality of logical addresses to a second plurality of sequential virtual addresses;

writing the first plurality of data units into a data buffer based on the first plurality of sequential virtual addresses;

writing the second plurality of data units into the data buffer based on the second plurality of sequential virtual addresses, wherein the first and second plurality of data units are written into sequential memory addresses of the data buffer;

mapping the first plurality of virtual addresses and the second plurality of virtual addresses to a plurality of physical addresses; and

writing the first and second plurality of data units in the data buffer into the memory block at the plurality of physical addresses in one write operation.

17. The method of claim 16, wherein the first plurality of data units is a first record, and the second plurality of data units is a second record.

18. The method of claim 16, wherein each data unit in the first plurality of data units and each data unit in the second plurality of data units is a page of data.