Modular command structure for memory and memory system

• US 7,904,639 B2
• Filed: 08/17/2007
• Issued: 03/08/2011
• Est. Priority Date: 08/22/2006
• Status: Active Grant

• Current Assignee: Mosaid Technologies Incorporated (MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management))
• Original Assignee: Mosaid Technologies Incorporated (MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management))
• Inventors: Oh, HakJune, Pyeon, Hong Beom, Kim, Jin-Ki
• Primary Examiner(s): Thomas; Shane M
• Application Number:
  US11/840,692
• Publication Number:
  US 20080052449A1
• Time in Patent Office: 1,299 Days
• Field of Search: 711/103, 711/157, 711/E12.003
• US Class Current: 711/103
• CPC Class Codes: G06F 13/1678 using bus width
• CPC Class Codes: G11C 7/10 Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• CPC Class Codes: G11C 7/1045 Read-write mode select circuits
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A system including a memory system and a memory controller is connected to a host system. The memory system has at least one memory device storing data. The controller translates the requests from the host system to one or more separatable commands interpretable by the at least one memory device. Each command has a modular structure including an address identifier for one of the at least one memory devices and a command identifier representing an operation to be performed by the one of the at least one memory devices. The at least one memory device and the controller are in a series-connection configuration for communication such that only one memory device is in communication with the controller for input into the memory system. The memory system can include a plurality of memory devices connected to a common bus.

Claims

1. A system comprising:

a memory system including a plurality of memory devices for storing data;

a processor for managing a request for access to the memory system; and

a controller for translating the request from the processor to a plurality of separatable commands of a modular structure interpretable by at least one of the plurality of memory devices, the plurality of separatable commands comprising an address identifier for the at least one of the plurality of memory devices and a command identifier representing an operation to be performed by the at least one of the plurality of memory devices, the plurality of memory devices and the controller being in a series-connection for communication,

the at least one of the plurality of memory devices including at least two memory banks,

the address identifier including a device address for the at least one of the plurality of memory devices and a bank address for at least one of the at least two memory banks,

the controller being configured to produce the plurality of separatable commands for each of the at least two memory banks to interleave issuance of the plurality of separatable commands, so that the at least two memory banks are concurrently processing the issued plurality of separatable commands.

2. The system of claim 1, wherein the plurality of memory devices in the memory system are connected to a common bus.

3. The system of claim 1, wherein the plurality of memory devices in the memory system are series-interconnected.

4. The system of claim 1, wherein the at least one of the plurality of memory devices comprises a flash memory device.

5. The system of claim 4, wherein the flash memory device comprises a NAND flash memory device.