System and method for providing data redundancy after reducing memory writes

• US 7,904,672 B2
• Filed: 11/19/2007
• Issued: 03/08/2011
• Est. Priority Date: 12/08/2006
• Status: Active Grant

• Current Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Original Assignee: SandForce, Inc. (Broadcom, Inc.)
• Inventors: Danilak, Radoslav
• Primary Examiner(s): Nguyen; Hiep T
• Application Number:
  US11/942,629
• Publication Number:
  US 20080141055A1
• Time in Patent Office: 1,205 Days
• Field of Search: None
• US Class Current: 711/154
• CPC Class Codes: G06F 11/1072 in multilevel memories
• CPC Class Codes: G06F 11/1076 Parity data used in redundant arrays of independent storages, e.g. in RAID systems
• CPC Class Codes: G06F 11/108 Parity data distribution in semiconductor storages, e.g. in SSD
• CPC Class Codes: G06F 12/00 Accessing, addressing or allocating within memory systems or architectures digital input from, or digital output to record carriers, e.g. to disk storage units, G06F3/06
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 13/1668 Details of memory controller
• CPC Class Codes: G06F 2211/1073 Problems due to wear-out failures in RAID systems
• CPC Class Codes: G06F 2211/1092 Single disk raid, i.e. RAID with parity on a single disk
• CPC Class Codes: G06F 2211/1095 Writes number reduction, i.e. reducing the number of writes in a RAID array with parity
• CPC Class Codes: G06F 3/0613 in relation to throughput
• CPC Class Codes: G06F 3/0616 in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/065 Replication mechanisms
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0661 Format or protocol conversion arrangements
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays
• CPC Class Codes: G06F 3/0689 Disk arrays, e.g. RAID, JBOD
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents

Abstract

A system, method, and computer program product are provided for providing data redundancy in a plurality of storage devices. In operation, a number of writes to a plurality of storage devices is reduced. Additionally, after the reducing, data redundancy is provided utilizing a data redundancy scheme.

Claims

1. A method, comprising:

receiving writes from a computer via a standard storage subsystem interface;

reducing a number of the received writes;

implementing, via a disk controller, a data redundancy scheme comprising storing data associated with the reduced number of writes in a plurality of primary flash memories and storing computed redundant information in at least one redundant flash memory; and

wherein the disk controller is enabled to operate without a loss of data in the presence of at least a single failure of any of the flash memories.

2. The method as recited in claim 1, wherein the data redundancy scheme includes a redundant array of independent disks (RAID) data redundancy scheme.

3. The method as recited in claim 2, wherein the data redundancy scheme includes a redundant array of independent disks (RAID)-5 data redundancy scheme.

4. The method as recited in claim 2, wherein the data redundancy scheme includes a redundant array of independent disks (RAID)-6 data redundancy scheme.

5. The method as recited in claim 1, wherein the standard storage subsystem interface comprises a SATA interface.

6. The method as recited in claim 5, wherein the disk controller is included in a disk drive.

7. The method as recited in claim 1, wherein the storage subsystem interface comprises a SAS interface.

8. The method as recited in claim 7, wherein the disk controller is included in a disk drive.

9. The method as recited in claim 1, wherein at least one of the flash memories comprises NAND flash memory.

10. The method as recited in claim 9, wherein the NAND flash memory includes single-level cell (SLC) NAND flash memory.

11. The method as recited in claim 9, wherein the NAND flash memory includes multi-level cell (MLC) NAND flash memory.

12. The method as recited in claim 1, wherein the flash memories are included in a disk drive.

13. The method as recited in claim 1, and further comprising detecting a disconnection of a power source of the disk controller.

14. The method as recited in claim 13, and further comprising providing power to the disk controller, in response to the detection of the disconnection of the power source.

15. The method as recited in claim 14, wherein power is provided to the disk controller until at least a point when no data loss will occur as a result of the disconnection of the power source.

16. The method as recited in claim 15, wherein the power is provided utilizing a capacitor.

17. The method as recited in claim 15, wherein the power is provided utilizing a battery.

18. The method as recited in claim 1, wherein the disk controller and the flash memories are included in a disk drive.

19. A computer program product embodied on a computer readable medium, comprising:

computer code for reducing a number of writes to a storage subsystem;

computer code for providing data redundancy utilizing a data redundancy scheme, after the reducing; and

wherein the writes are received from a computer via a standard storage subsystem interface, the data redundancy scheme is implemented by a disk controller and comprises storing data associated with the reduced number of writes in a plurality of primary flash memories and storing computed redundant information in at least one redundant flash memory, and the disk controller is enabled to operate without a loss of data in the presence of at least a single failure of any of the flash memories.

20. An apparatus, comprising:

a circuit enabled to receive writes from a computer via a standard storage subsystem interface, and further enabled to reduce a number of the received writes;

a disk controller that implements a data redundancy scheme comprising storing data associated with the reduced number of writes in a plurality of primary flash memories and storing computed redundant information in at least one redundant flash memory; and

wherein the disk controller is enabled to operate without a loss of data in the presence of at least a single failure of any of the flash memories.

21. The apparatus as recited in claim 20, and further comprising a the primary and the redundant flash memories.