Asynchronous power saving computer

• US 7,904,695 B2
• Filed: 02/16/2006
• Issued: 03/08/2011
• Est. Priority Date: 02/16/2006
• Status: Expired due to Fees

• Current Assignee: Array Portfolio LLC
• Original Assignee: VNS Portfolio LLC
• Inventors: Moore, Charles H.
• Primary Examiner(s): TSENG, CHENG YUAN
• Application Number:
  US11/355,513
• Publication Number:
  US 20070192646A1
• Time in Patent Office: 1,846 Days
• Field of Search: 340/286, 345/501, 710/100, 710/18, 710/306, 710/307, 710/316, 712/10, 712/11, 712/13, 712/15, 712/18, 712/210, 712/22, 712/220, 712/23, 712/35, 712/320, 712/323, 327/536, 327/108, 327/175, 327/538
• US Class Current: 712/16
• CPC Class Codes: G06F 1/3209 Monitoring remote activity, e.g. over telephone lines or network connections
• CPC Class Codes: G06F 1/3243 Power saving in microcontroller unit
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A computer array (10) has a plurality of computers (12). The computers (12) communicate with each other asynchronously, and the computers (12) themselves operate in a generally asynchronous manner internally. When one computer (12) attempts to communicate with another it goes to sleep until the other computer (12) is ready to complete the transaction, thereby saving power and reducing heat production. A slot sequencer (42) in each of the computers produces a timing pulse to cause the computer (12) to execute a next instruction. However, when the present instruction is a read or write type instruction, the slot sequencer does not produce the pulse until an acknowledge signal (86) starts it. The acknowledge signal (86) is produced when it is recognized that the communication has been completed by the other computer (12).

Claims

1. A computer, comprising:

a processor for executing a plurality of instructions from an instruction area; and

a sequencer for providing a pulse to advance from a presently executed instruction to a next instruction of said plurality of instructions;

wherein

each of said plurality of instructions includes a bit for providing an input to the sequencer such that the sequencer is triggered into providing the pulse when the bit is set;

said computer is one of an array of computers integrated on a single chip;

when said bit for providing the input to the sequencer is not set then the sequencer is not triggered into providing the pulse;

when said bit for providing the input to the sequencer is not set then a first communications status line is set between the computer and a second computer;

the sequencer includes a ring oscillator having an odd number of inverting logic elements connected in a ring;

the sequencer has a first input terminal operative to trigger the sequencer into providing the pulse responsive to the bit being set; and

the sequencer has a second input terminal operative to trigger the sequencer into providing the pulse responsive to an acknowledgment signal indicating completion of a communication between the computer and a second computer on the chip.

2. The computer of claim 1, wherein:

the bit is set when it is a ‘

1’

.

3. The computer of claim 1, wherein:

the plurality of instructions are part of a larger instruction word.

4. The computer of claim 1, wherein:

said first communications status line is a write line.

5. The computer of claim 1, wherein:

said first communications status line is a read line.

6. The computer of claim 1, wherein:

when a second communications status line is set then data is transferred between the computer and the second computer.

7. The computer of claim 6, wherein:

data is transferred from the computer to the second computer.

8. The computer of claim 6, wherein:

the data includes an instruction.

9. The computer of claim 6, wherein:

when the second communications status line is set then the acknowledgement signal is provided to the sequencer such that the sequencer is triggered into providing the pulse.

10. A method for causing a computer to temporarily reduce its power consumption, comprising:

(a) causing the computer to stop operation when a communication is attempted with another computer; and

(b) causing the computer to resume operation when completion of the communication with the another computer is acknowledged; and

wherein

a sequencer produces a pulse to cause execution of each of a plurality of instructions;

no such pulse is immediately produced when the communication is attempted with the another computer;

both the computer and the another computer are on a single chip;

the sequencer includes a ring oscillator having an odd number of inverting logic elements connected in a ring;

the sequencer has a first input terminal operative to trigger the sequencer into providing the pulse responsive to a bit of one of the instructions being set;

the sequencer has a second input terminal operative to trigger the sequencer into providing the pulse responsive to an acknowledgment signal indicating the completion of the communication between the computer and the another computer;

when the bit for providing the input to the sequencer is not set then the sequencer is not triggered into providing the pulse; and

when the bit for providing the input to the sequencer is not set then a first communications status line is set between the computer and the another computer.

11. The method of claim 10, wherein:

when the computer stops operation it also alters the status of the first communications status line between the computer and the another computer.

12. The method of claim 10, wherein:

there are two communications status lines between the computer and the another computer; and

communication with the another computer is acknowledged when each of said two communications status lines are set to a same status.

13. The method of claim 10, wherein:

when the computer operation is stopped then the first communications status line of two communications status lines between the computer and the another computer is set; and

when the second communications status line is set then data is communicated and then operation of the computer is resumed.

14. The method of claim 10, wherein:

when the completion of the communication with the another computer is acknowledged then the acknowledgment signal is generated and the sequencer provides the pulse to cause execution of a next instruction.

15. In a computer for executing instructions wherein at least some of the instructions are communication instructions for causing the computer to communicate with an outside entity, an improvement comprising:

means for causing the computer to stop when a communication instruction is attempted; and

means for causing the computer to restart when the communication instruction is completed; and

wherein

the means for causing the computer to stop includes a pulse generating apparatus for generating a pulse when each of the instructions is executed, except that when the instruction being attempted is one of the communication instructions then no such pulse is generated;

the means for causing the computer to restart when the communication instruction is completed includes a means for causing the pulse generating apparatus to generate the pulse;

the pulse generating apparatus is caused to generate the pulse when the outside entity acknowledges completion of a communication;

the pulse generating apparatus includes a ring oscillator having an odd number of inverting logic elements connected in a ring;

the pulse generating apparatus has a first input terminal operative to trigger the pulse generating apparatus into generating the pulse responsive to a bit of the instruction being attempted being set;

the pulse generating apparatus has a second input terminal operative to trigger the pulse generating apparatus into generating the pulse responsive to an acknowledgment signal indicating completion of the communication between the computer and the outside entity;

when said bit for providing the input to the pulse generating apparatus is not set then the pulse generating apparatus is not triggered into generating the pulse;

when said bit for providing the input to the pulse generating apparatus is not set then a first communications status line is set between the computer and the outside entity;

both the computer and the outside entity are on a single chip; and

the outside entity is another computer.