System abstraction layer, processor abstraction layer, and operating system error handling

• US 7,904,751 B2
• Filed: 07/28/2003
• Issued: 03/08/2011
• Est. Priority Date: 12/30/1999
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Quach, Nhon T., Lint, Bernard J., Marisetty, Suresh, Ayyar, Mani
• Primary Examiner(s): Chu; Gabriel L
• Application Number:
  US10/628,769
• Publication Number:
  US 20040019835A1
• Time in Patent Office: 2,780 Days
• Field of Search: None
• US Class Current: 714/10
• CPC Class Codes: G06F 11/0724 in a multiprocessor or a multi-core unit multiprocessors per se G06F15/80
• CPC Class Codes: G06F 11/0793 Remedial or corrective actions recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40

Abstract

Systems and methods for error handling are disclosed. The systems and methods may be utilized for single or multiple processor computer systems to handle errors in a coordinated manner between hardware and any firmware or software layers. A computer system includes a non volatile memory and at least one processor. A firmware error handling routine is stored on the non volatile memory. The firmware error handling routine is for handling errors. Each of the at least one processors detects errors. Each processor executes the firmware error handling routine on detecting an error. The executed firmware error handling routine handles the error. The executed firmware error handling routine also logs error information to a log.

The systems and methods provide for coordinated error handling that enhance error recovery, provide error containment and maintain system availability.

Claims

1. A processor comprising:

first logic to detect an error;

second logic to attempt to correct a detected error; and

a first interface to a first memory external to the processor that stores a set of procedures to access the processor across different processor implementations and at least a first software error handling routine to be invoked by the processor via the first interface when the second logic cannot correct the detected error.

2. The processor of claim 1, wherein the first memory further stores a second software error handling routine to be invoked by the processor when the first software error handling routine cannot correct the detected error.

3. The processor of claim 2, further comprising:

a second interface to a second memory that stores an operating system, wherein the operating system includes a third software error handling routine to be invoked by the processor when the second software error handling routine cannot correct the detected error.

4. The processor of claim 2, wherein the first interface couples to a second memory that stores an operating system, wherein the operating system includes a third software error handling routine to be invoked by the processor when the second software error handling routine cannot correct the detected error.

5. The processor of claim 1, wherein the second logic is adapted to correct a single bit error correcting code (ECC) error.

6. The processor of claim 1, wherein the processor is to signal the memory with a correctable machine check (CMC) signal to inform the memory that an error has occurred and been corrected when the second logic corrects a detected error.

7. The processor of claim 1, wherein upon the first logic detecting an error generates a machine check abort (MCA) to indicate that a hardware error or error has occurred.

8. The processor of claim 1, wherein the first software error handling routine is to:

determine if the detected error is processor related;

save minimal state information; and

attempt to correct the detected error.

9. A system comprising:

a processor;

a first memory coupled to the processor, the first memory to store at least a first firmware error handling routine to be invoked by the processor to attempt to correct a detected error when the processor cannot correct the detected error and a second firmware error handling routine to be invoked by the processor after the first firmware error handling routine has been invoked; and

a display coupled to the processor.

10. The system of claim 9, wherein the first firmware error handling routine is to save a status of the detected error and at least a portion of the processor'"'"'s state information.

11. The system of claim 10, wherein the first memory further to store a second firmware error handling routine to be invoked by the processor to attempt to correct the detected error when the first firmware error handling routine cannot correct the detected error.

12. The system of claim 10, wherein the second firmware error handing routine to determine the severity of the detected error by analyzing the processor'"'"'s saved state information and the detected error, and to save additional state information.

13. The system of claim 10, further comprising:

a second memory coupled to the processor, the second memory to store an operating system that includes a third error handling routine that is invoked by the processor to attempt to correct the detected error when the first and second firmware error handling routines cannot correct the detected error.

14. The system of claim 13, wherein the processor is reset if the detected error cannot be corrected by the third error handling routine.

15. The system of claim 14, wherein the processor is to detect the detected error.

16. A system comprising:

a non-volatile memory to store firmware including a processor abstraction layer (PAL) and a system abstraction layer (SAL), wherein the PAL provides an interface to access the processor across different processor implementations and a first error handling routine and the SAL isolates an operating system from implementation differences in the system and provides a second error handling routine to be invoked if the first error handling routine cannot correct a detected error; and

a processor coupled to the non-volatile memory, the processor to execute the first and second error handling routines to attempt to correct an error.

17. The system of claim 16, wherein the first error handling routine to save a status of the error and at least a portion of state information associated with the error.

18. The system of claim 17, wherein the second error handing routine to determine the severity of the detected error by analyzing the saved state information and the error, and to save additional state information.

19. The system of claim 18, further comprising:

a second memory coupled to the processor, the second memory to store an operating system that includes a third error handling routine that is invoked by the processor to attempt to correct the error when the first and second error handling routines cannot correct the detected error.

20. A processor comprising:

first logic to detect an error;

second logic to attempt to correct a detected error; and

a first external interface to a first memory that stores at least a first software error handling routine to be invoked by the processor via the first interface when the second logic cannot correct the detected error and a second software error handling routine to be invoked by the processor when the first software error handling routine cannot correct the detected error.