Soft-input soft-output decoder for nonvolatile memory

• US 7,904,783 B2
• Filed: 09/28/2006
• Issued: 03/08/2011
• Est. Priority Date: 09/28/2006
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Corporation (Western Digital Corporation)
• Inventors: Conley, Kevin M., Brandman, Yigal
• Primary Examiner(s): Baker; Stephen M
• Application Number:
  US11/536,327
• Publication Number:
  US 20080082897A1
• Time in Patent Office: 1,622 Days
• Field of Search: 714/755, 714/773, 714/778, 714/780
• US Class Current: 714/755
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G06F 11/1072 in multilevel memories
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 2029/0411 Online error correction

Abstract

In a nonvolatile memory system, data is read from a memory array and used to obtain likelihood values, which are then provided to a soft-input soft-output decoder. The soft-input soft-output decoder calculates output likelihood values from input likelihood values and from parity data that was previously added according to an encoding scheme.

Claims

1. A nonvolatile memory system comprising:

a memory array including a plurality of cells for storing a modulated plurality of data bits and a plurality of parity bits that are calculated from the plurality of data bits according to an encoding scheme;

a demodulator for reading the plurality of cells and deriving raw likelihood values corresponding to the plurality of data bits and the plurality of parity bits, wherein the demodulator is further operable to read each memory cell using a predetermined pattern of read operations, the pattern having at least one area of higher density and one area of lower density; and

a decoder for receiving the raw likelihood values and calculating output likelihood values therefrom using a decoding scheme that corresponds to the encoding scheme.

2. The nonvolatile memory system of claim 1 wherein the demodulator is further operable to resolve a number of read states per cell that is greater than the number of program states used to program the plurality of cells.

3. The nonvolatile memory system of claim 1 wherein the encoding scheme uses turbo coding.

4. The nonvolatile memory system of claim 1 wherein the encoding scheme uses a Low Density Parity Check (LDPC) code.

5. The nonvolatile memory system of claim 1 further comprising a converter for converting a soft input to a hard output.

6. The nonvolatile memory system of claim 1 wherein the decoder is further operable to subsequently calculate additional likelihood values from the output likelihood values using the decoding scheme.

7. The nonvolatile memory system of claim 6 wherein the decoder is further operable to calculate additional likelihood values in two or more iterations, the iterations performed until a predetermined condition is met.

8. The nonvolatile memory system of claim 7 further comprising a hard-input hard-output decoder for receiving the output likelihood values from the decoder, the hard-input hard-output decoder being configured for determining when the predetermined condition is met.

9. A nonvolatile memory system comprising:

a nonvolatile memory array for storing two or more bits in an individual memory cell; and

a demodulator for deriving an individual likelihood value for each of the two or more bits stored in the individual memory cell,

wherein the demodulator is operable to read the individual memory cell using a predetermined pattern of read operations, the pattern having at least one area of higher density and one area of lower density.

10. The nonvolatile memory system of claim 9 further comprising a lookup table for storing the individual likelihood values for each of the two or more bits.

11. The nonvolatile memory system of claim 9 wherein the two or more bits include at least one parity bit that was added according to an encoding scheme.

12. The nonvolatile memory system of claim 9 wherein the demodulator is further operable to derive the individual likelihood values by reading the individual memory cell with a resolution that identifies more than the number of program states of the individual memory cell.

13. The nonvolatile memory system of claim 9 further comprising a soft-input soft-output decoder for receiving the individual likelihood values as input and calculating output likelihood values from the individual likelihood values.

14. A nonvolatile memory system comprising:

an array of nonvolatile memory cells for individually programming to one of two or more threshold voltage ranges that represent two or more states; and

a demodulator for resolving an individual cell threshold voltage to an identified one of the two or more threshold voltage ranges and further resolving the individual cell threshold voltage within the identified threshold voltage range by providing a higher density of read operations for a first portion of the identified threshold voltage range than at for a second portion of the identified threshold voltage range, the demodulator being further configured for deriving likelihood values from the read operations for the first and second portions.

15. The nonvolatile memory system of claim 14 further comprising a soft-input soft-output decoder for receiving the likelihood values as input.

16. The nonvolatile memory system of claim 15 wherein the soft-input soft-output decoder is further operable to calculate output likelihood values in multiple iterations until a predetermined condition is met.

17. The nonvolatile memory system of claim 16 further comprising a soft-hard converter for converting the output likelihood values to hard output values when the predetermined condition is met.

18. The nonvolatile memory system of claim 16 further comprising a hard-input hard-output decoder for receiving the output likelihood values from the soft-input soft-output decoder, the hard-input hard-output decoder being configured for determining when the predetermined condition is met.

19. The nonvolatile memory system of claim 14 wherein nonvolatile memory cells are further individually programmable to four or more threshold voltage ranges that represent four or more states to store two or more bits, the demodulator being configured for deriving likelihood values for each of the two or more bits.