Techniques for detecting and correcting errors in a memory device

• US 7,904,789 B1
• Filed: 03/31/2006
• Issued: 03/08/2011
• Est. Priority Date: 03/31/2006
• Status: Active Grant

• Current Assignee: Intellectual Ventures Funding LLC (Intellectual Ventures LLC)
• Original Assignee: Intellectual Ventures Funding LLC (Intellectual Ventures LLC)
• Inventors: Rozas, Guillermo
• Primary Examiner(s): Baderman; Scott T
• Assistant Examiner(s): Ahmed; Enam
• Application Number:
  US11/395,710
• Time in Patent Office: 1,803 Days
• Field of Search: 714/763
• US Class Current: 714/763
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G11C 2029/0411 Online error correction

Abstract

A technique for detecting and correcting errors in a memory device, in accordance with one embodiment of the present invention, includes a data storage area arranged in a plurality of blocks, wherein each block contains a plurality of words. The memory device also includes an error detection/correction storage area for storing error detection/correction bytes corresponding to each word in each block and error detection words corresponding to each block.

Claims

1. A memory device comprising:

a data storage area of memory cells arranged in a plurality of blocks, wherein a block includes a plurality of words; and

an error detection/correction storage area of memory cells configured to store a) error detection/correction bytes and b) error detection words, wherein an error detection/correction byte is calculated from a corresponding word in the block and wherein a respective bit of the error detection word is calculated from respective bits in the corresponding words in the block.

2. The memory device of claim 1, wherein the error detection/correction byte is stored in a corresponding word-wise extension of the data storage area.

3. The memory device of claim 2, wherein the error detection word is stored in a bit-wise extension of the data storage area.

4. The memory device of claim 1, wherein a respective chunk of the corresponding error detection word is stored in the corresponding word-wise extension of the data storage area.

5. The memory device of claim 1, further comprising an error detection/correction logic, coupled to the data storage area and the error detection/correction storage area, configured to generate the error detection/correction bytes.

6. The memory device of claim 1, further comprising an error detection/correction logic, coupled to the data storage area and the error detection/correction storage area, configured to generate the error detection words.

7. The memory device of claim 1, further comprising an error detection/correction logic, coupled to the data storage area and the error detection/correction storage area, configured to detect and correct a single bit error in a word in the data storage area utilizing a corresponding error detection/correction byte.

8. The memory device of claim 1, further comprising an error detection/correction logic, coupled to the data storage area and the error detection/correction storage area, configured to detect and correct a double-bit error in a single word in a given block of the data storage area utilizing a corresponding error detection/correction byte of the given block in combination with an error detection word of the given block.

9. The memory device of claim 1, wherein the error detection/correction byte comprises an error correction code (ECC) byte of a corresponding word in the data storage area.

10. The memory device of claim 1, wherein the error detection word comprises a parity bit for respective bits in the corresponding words of a block in the data storage area.

11. A method of writing data, the method comprising:

computing, by an error detection/correction logic circuit, an error detection/correction byte for a word in a block;

computing, by the error detection/correction logic circuit, an error detection word wherein a respective bit in the error detection word is calculated from respective bits of the plurality of words in the block;

computing, by the error detection/correction logic circuit, an error detection/correction byte for the error detection word; and

storing the error detection/correction byte for the word in the block, the error detection word, and the error detection/correction byte for the error detection word in a memory device.

12. The method of claim 11, further comprising storing the word in a data storage area of the memory device.

13. The method of claim 11, further comprising storing the error detection/correction byte for the word, the error detection word for the plurality of words in a block including the word, and the error detection/correction byte for the error detection word in an extension of the data storage area.

14. The method of claim 13, wherein the error detection/correction byte of the word is stored in a word-wise portion of the extension of the data storage area corresponding to the word.

15. The method of claim 14, wherein the error detection word and the error detection/correction byte of the error detection word are stored in a bite-wise portion of the extension of the data storage area.

16. The method of claim 14, wherein a plurality of chunks of the error detection word and the error detection/correction byte of the error detection word are stored in respective word-wise portions of the extension of the data storage area corresponding to the words in the block.

17. The method of claim 11, wherein:

the error detection/correction byte for the word is generated by computing an error correction code (ECC) for the word; and

the error detection/correction byte for the error detection word is generated by computing an ECC for the error detection word.

18. The method of claim 17, wherein the error detection word is generated by computing a parity bit for respective bits in the corresponding words in the block.

19. A method comprising:

reading a) a block of data, b) corresponding error detection/correction bytes and c) a corresponding error detection word, wherein the error detection/correction byte is calculated from a corresponding word in the block of data and wherein a respective bit of the error detection word is calculated from respective bits in the words in the block of data;

detecting, by an error detection/correction logic circuit, errors in a given word of the block of data using a) a given one of the error detection/correction bytes computed from the given word and b) the error detection word;

correcting, by the error detection/correction logic circuit, a single-bit error in the given word using the given one of the error detection/correction bytes, if a single-bit error in the word is detected; and

correcting, by the error detection/correction logic circuit, a double-bit error in the given word using a) the given one of the error detection/correction bytes and b) the error detection word, if a double-bit error in the word is detected.

20. The method of claim 19, wherein said detecting errors further comprises:

reading the words in the block, the error detection/correction byte for the word in the block, the error detection word for the block and the error detection/correction byte for the error detection word;

checking a word against the corresponding error detection/correction byte; and

checking the error detection word against the corresponding error detection/correction byte.

21. The method of claim 19, wherein correcting the single-bit error further comprises:

correcting the error in the given word; and

storing the corrected word.

22. The method of claim 19, wherein correcting the double-bit error further comprises:

re-computing the error detection word from the words in the block after single bit error correction, if necessary;

comparing the re-computed error detection word to the error detection word as read or as corrected by using single-bit error correction, if necessary;

correcting a given word by flipping a corresponding bit for any bit position in which the re-computed error detection word differs from the error detection word as read;

re-computing the error detection/correction byte corresponding to the corrected given word; and

storing the corrected given word and the re-computed error detection/correction byte.

23. The method of claim 22, further comprising re-computing, by the error detection/correction logic circuit, the error detection word from the words in the block, if the multi-bit error was in the error detection word.

24. The method of claim 19, wherein:

the error detection/correction byte for the word is generated by computing an error correction code (ECC) for the word; and

the error detection/correction byte for the error detection word is generated by computing an error correction code (ECC) for the error detection word.

25. The method of claim 20, wherein the error detection word is generated by computing a parity bit for respective bits in the corresponding words in the block.

26. A memory device comprising:

a means for computing an error detection/correction byte for a word in a block;

a means for computing an error detection word from respective bits in the corresponding words in the block;

a means for computing an error detection/correction byte for the error detection word; and

a means for storing the error detection/correction byte for the word in the block, the error detection word, and the error detection/correction byte for the error detection word in a data storage area.

27. The memory device of claim 26, further comprising:

a means for retrieving the error detection/correction byte for the word in the block, the error detection word, and the error detection/correction byte for the error detection word from the data storage area;

a means for detecting errors in a given word using a given error detection/correction byte corresponding to the given word and the error detection word;

a means for correcting a single-bit error in the given word using the given error detection/correction byte, if a single-bit error in the given word is detected; and

a means for correcting a double-bit error in the given word using the given error detection/correction byte corresponding to the given word and the error detection word, if a double-bit error in the given word is detected.

28. The memory device of claim 27, wherein:

the error detection/correction byte for the word comprises an error correction code (ECC);

the bits of the error detection word comprises a parity bit; and

the error detection/correction byte for the error detection word comprises an ECC.