Memory array with a pair of memory-cell strings to a single conductive pillar

• US 7,906,818 B2
• Filed: 03/13/2008
• Issued: 03/15/2011
• Est. Priority Date: 03/13/2008
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Pekny, Theodore T.
• Primary Examiner(s): Tran; Minh-Loan T
• Assistant Examiner(s): Sengdara; Vongsavanh
• Application Number:
  US12/047,414
• Publication Number:
  US 20090230454A1
• Time in Patent Office: 1,097 Days
• Field of Search: 257/324, 257/325, 257/390, 257/391, 257/E27.102, 257/E29.131, 257/E29.134, 257/E29.309
• US Class Current: 257/390
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/10 characterised by the top-view layout
• CPC Class Codes: H10B 43/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/30 characterised by the memory core region
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND

Abstract

Memory arrays and methods of forming memory arrays are disclosed. One such memory array has a first string of serially-coupled first memory cells and a second string of serially-coupled second memory cells sharing a single conductive pillar which forms a channel for both strings of serially-coupled memory cells. For example, a first memory cell can have a first control gate on the first side of the conductive pillar and a first charge trap interposed between the first side of the conductive pillar and the first control gate. A second memory cell can have a second control gate on the second side of the conductive pillar and a second charge trap interposed between the second side of the conductive pillar and the second control gate. The first and second charge traps are electrically isolated from each other and the first and second control gates can be electrically isolated from each other.

Claims

1. A memory array, comprising:

a first pair of electrically isolated activation lines formed on opposing sides of one or more conductive pillars;

a second pair of electrically isolated activation lines formed on opposing sides of the one or more conductive pillars; and

a plurality of charge storage nodes, wherein each charge storage node is interposed between a respective one of the conductive pillars and respective one of the activation lines;

wherein a memory cell formed at an intersection of a first one of the first pair of activation lines and a given one of the conductive pillars, and a memory cell formed at an intersection of a first one of the second pair of activation lines and the given one of the conductive pillars, form at least a portion of a first serially-coupled string of memory cells;

wherein a memory cell formed at an intersection of a second one of the first pair of activation lines and the given one of the conductive pillars, and a memory cell formed at an intersection of a second one of the second pair of activation lines and the given one of the conductive pillars, form at least a portion of a second serially- coupled string of memory cells; and

wherein the first one of the first pair of activation lines and the first one of the second pair of activation lines are formed on the same side of the given one of the conductive pillars.

2. The memory array of claim 1, further comprising a first select transistor coupled to a first end of the first serially-coupled string of memory cells and a first end of the second serially-coupled string of memory cells.

3. The memory array of claim 2, wherein the one or more conductive pillars are one or more first conductive pillars, wherein the first select transistor is formed at an intersection between a select line and a second conductive pillar coupled to an end of the given one of the first conductive pillars.

4. The memory array of claim 3, wherein second conductive pillar is further coupled to a source line.

5. The memory array of claim 2 further comprises a second select transistor coupled to a second end of the first serially-coupled string of memory cells and a second end of the second serially-coupled string of memory cells.

6. The memory array of claim 5, wherein the one or more conductive pillars are one or more first conductive pillars, wherein the second select transistor is formed at an intersection between a select line and a second conductive pillar coupled to a second end of the given one of the first conductive pillars.

7. The memory array of claim 6, wherein second conductive pillar is further coupled to a data line.

8. The memory array of claim 5, wherein the first select transistor selectively couples the first serially-coupled string of memory cells and the second serially-coupled string of memory cells to a source line and the second select transistor selectively couples the first serially-coupled string of memory cells and the second serially-coupled string of memory cells to a data line.

9. The memory array of claim 1, further comprising an isolation region interposed between the first and second ones of the first and second pairs of activation lines.

10. The memory array of claim 9, wherein the isolation region extends between the charge storage node interposed between the first one of the first pair of activation lines and the given one of the conductive pillars and the charge storage node interposed between the second one of the first pair of activation lines and the given one of the conductive pillars.

11. The memory array of claim 10, wherein the isolation region further extends between the charge storage node interposed between the first one of the second pair of activation lines and the given one of the conductive pillars and the charge storage node interposed between the second one of the second pair of activation lines and the given one of the conductive pillars.

12. A memory array, comprising:

a conductive pillar;

a data line selectively coupled to a first end of the conductive pillar;

a source line selectively coupled to a second end of the conductive pillar;

a memory cell of a first serially-coupled string of memory cells on a first side of the conductive pillar, comprising a first control gate interposed between the data line and the source line on-a the first side of the conductive pillar, and a first charge storage node interposed between the first control gate and the first side of the conductive pillar; and

a memory cell of a second, different serially-coupled string of memory cells on a second side of the conductive pillar, comprising a second control gate interposed between the data line and the source line on the second side of the conductive pillar, and a second charge storage node interposed between the second control gate and the second side of the conductive pillar, the second side of the conductive pillar opposing the first side of the conductive pillar.

13. The memory array of claim 12 further comprising a drain select transistor that selectively couples the data line to the first end of the conductive pillar and a source select transistor that selectively couples the source line to the second end of the conductive pillar.

14. The memory array of claim 13, wherein the conductive pillar is a first conductive pillar, wherein the drain select transistor is formed at an intersection between a drain select line and a second conductive pillar coupled between the data line and the first end of the first conductive pillar.

15. The memory array of claim 14, wherein the source select transistor is formed at an intersection between a source select line and a third conductive pillar coupled between the source line and the second end of the first conductive pillar.

16. A memory array, comprising:

a conductive pillar;

a data line selectively coupled to a first end of the conductive pillar;

a source line selectively coupled to a second end of the conductive pillar;

a first memory cell comprising a first control gate interposed between the data line and the source line on a first side of the conductive pillar, and a first charge storage node interposed between the first control gate and the first side of the conductive pillar;

a second memory cell comprising a second control gate interposed between the data line and the source line on a second side of the conductive pillar, and a second charge storage node interposed between the second control gate and the second side of the conductive pillar, the second side of the conductive pillar opposing the first side of the conductive pillar;

a third memory cell comprising a third control gate interposed between the first control gate and the source line on the first side of the conductive pillar, and a third charge storage node interposed between the third control gate and the first side of the conductive pillar; and

a fourth memory cell comprising a fourth control gate interposed between the second control gate and the source line on the second side of the conductive pillar, and a fourth charge storage node interposed between the fourth control gate and the second side of the conductive pillar;

wherein the first and third memory cells are serially coupled by the conductive pillar to form at least a portion of a first serially-coupled string of memory cells and the second and fourth memory cells are serially coupled by the conductive pillar to form at least a portion of a second serially-coupled string of memory cells.

17. The memory array of claim 16 further comprising an isolation region interposed between the first and second control gates and between the first and second charge storage nodes, the isolation region further interposed between the third and fourth control gates and between the third and fourth charge storage nodes.