Chip structure and process for forming the same

• US 7,906,849 B2
• Filed: 02/18/2008
• Issued: 03/15/2011
• Est. Priority Date: 12/21/1998
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Megica Corporation (Chipbond Technology Corporation)
• Inventors: Huang, Ching-Cheng, Lin, Mou-Shiung, Lee, Jin-Yuan
• Primary Examiner(s): Zarneke; David A
• Application Number:
  US12/032,707
• Publication Number:
  US 20080136034A1
• Time in Patent Office: 1,121 Days
• Field of Search: 257/759, 257/758, 257/750, 257/E23.151, 257/E23.145, 257/E23.142, 257/E23.011, 257/E23.012, 257/E23.02
• US Class Current: 257/759
• CPC Class Codes: H01L 21/768 Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
• CPC Class Codes: H01L 21/76807 for dual damascene structures
• CPC Class Codes: H01L 21/76838 characterised by the formation and the after-treatment of the conductors etching for patterning the conductors H01L21/3213
• CPC Class Codes: H01L 21/76885 By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
• CPC Class Codes: H01L 2224/0231 Manufacturing methods of the redistribution layers
• CPC Class Codes: H01L 2224/02311 Additive methods
• CPC Class Codes: H01L 2224/02313 Subtractive methods
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/05548 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13 of an individual bump connector
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 23/522 including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• CPC Class Codes: H01L 23/5222 Capacitive arrangements or effects of, or between wiring layers other capacitive arrangements H01L23/642
• CPC Class Codes: H01L 23/5223 Capacitor integral with wiring layers
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/5228 Resistive arrangements or effects of, or between, wiring layers other resistive arrangements H01L23/647
• CPC Class Codes: H01L 23/5286 Arrangements of power or ground buses
• CPC Class Codes: H01L 23/5329 Insulating materials
• CPC Class Codes: H01L 23/53295 Stacked insulating layers
• CPC Class Codes: H01L 23/60 : Protection against electrostatic charges or discharges, e.g. Faraday shields
• CPC Class Codes: H01L 24/02 : Bonding areas on insulating substrates, e.g. chip carriers, H01L23/49816, H01L23/49838, H01L23/5389; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/10 : Bump connectors bumps on insulating substrates, e.g. chip carriers, H01L23/49816; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 27/0251 : for MOS devices
• CPC Class Codes: H01L 27/0676 : comprising combinations of diodes, or capacitors or resistors
• CPC Class Codes: H01L 27/08 : including only semiconductor components of a single kind
• CPC Class Codes: H01L 28/10 : Inductors
• CPC Class Codes: H01L 28/20 : Resistors
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/04953 : TaN
• CPC Class Codes: H01L 2924/12044 : OLED
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15174 : in different layers of the multilayer substrate
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: Y10T 29/49124 : On flat or curved insulated base, e.g., printed circuit, etc.
• CPC Class Codes: Y10T 29/49204 : Contact or terminal manufacturing

Abstract

A chip structure comprises a substrate, a first built-up layer, a passivation layer and a second built-up layer. The substrate includes many electric devices placed on a surface of the substrate. The first built-up layer is located on the substrate. The first built-up layer is provided with a first dielectric body and a first interconnection scheme, wherein the first interconnection scheme interlaces inside the first dielectric body and is electrically connected to the electric devices. The first interconnection scheme is constructed from first metal layers and plugs, wherein the neighboring first metal layers are electrically connected through the plugs. The passivation layer is disposed on the first built-up layer and is provided with openings exposing the first interconnection scheme. The second built-up layer is formed on the passivation layer. The second built-up layer is provided with a second dielectric body and a second interconnection scheme, wherein the second interconnection scheme interlaces inside the second dielectric body and is electrically connected to the first interconnection scheme. The second interconnection scheme is constructed from at least one second metal layer and at least one via metal filler, wherein the second metal layer is electrically connected to the via metal filler. The thickness, width, and cross-sectional area of the traces of the second metal layer are respectively larger than those of the first metal layers.

Claims

1. A chip comprising:

a silicon substrate;

a transistor in or on said silicon substrate;

a first copper layer over said silicon substrate;

a second copper layer over said first copper layer and over said silicon substrate;

a dielectric layer between said first and second copper layers;

a copper plug in said dielectric layer and between said first and second copper layers, wherein said copper plug connects said first and second copper layers;

a first conductive pad over said silicon substrate;

a second conductive pad over said silicon substrate;

a passivation layer over said first and second copper layers and over said dielectric layer, wherein said passivation layer comprises a nitride layer, wherein a first opening in said passivation layer is over a first contact point of said first conductive pad, and said first contact point is at a bottom of said first opening, wherein said first opening has a width between 0.5 and 20 micrometers, and wherein a second opening in said passivation layer is over a second contact point of said second conductive pad, and said second contact point is at a bottom of said second opening;

a first polymer layer on said passivation layer, wherein a third opening in said first polymer layer is over said first contact point, and a fourth opening in said first polymer layer is over said second contact point, wherein said first polymer layer has a thickness between 1 and 100 micrometers; and

a metallization structure on said first polymer layer and on said first and second contact points, wherein said first contact point is connected to said second contact point through said metallization structure, wherein said metallization structure comprises a titanium-containing layer on said first polymer layer and an electroplated copper layer over said titanium-containing layer, wherein said electroplated copper layer has a sidewall not covered by said titanium-containing layer.

2. The chip of claim 1, wherein said first polymer layer comprises polyimide.

3. The chip of claim 1, wherein said first polymer layer comprises benzocyclobutene (BCB).

4. The chip of claim 1 further comprising a second polymer layer on said metallization structure.

5. The chip of claim 4, wherein said second polymer layer comprises polyimide.

6. The chip of claim 4, wherein said second polymer layer comprises benzocyclobutene (BCB).

7. The chip of claim 1, wherein said titanium-containing layer comprises a titanium-tungsten alloy.

8. The chip of claim 1, wherein said passivation layer further comprises an oxide layer.

9. The chip of claim 1, wherein said metallization structure on said first polymer layer has a thickness between 1 and 50 micrometers.

10. The chip of claim 1, wherein said metallization structure is further on a sidewall of said first opening and contacts a region of said passivation layer.

11. A chip comprising:

a silicon substrate;

a transistor in or on said silicon substrate;

a first copper layer over said silicon substrate;

a second copper layer over said first copper layer and over said silicon substrate;

a dielectric layer between said first and second copper layers;

a copper plug in said dielectric layer and between said first and second copper layers, wherein said copper plug connects said first and second copper layers;

a first conductive pad over said silicon substrate;

a second conductive pad over said silicon substrate;

a passivation layer over said first and second copper layers and over said dielectric layer, wherein said passivation layer comprises a nitride layer, wherein a first opening in said passivation layer is over a first contact point of said first conductive pad, and said first contact point is at a bottom of said first opening, wherein said first opening has a width between 0.5 and 20 micrometers, and wherein a second opening in said passivation layer is over a second contact point of said second conductive pad, and said second contact point is at a bottom of said second opening;

a first polymer layer on said passivation layer, wherein a third opening in said first polymer layer is over said first contact point, and a fourth opening in said first polymer layer is over said second contact point, wherein said first polymer layer has a thickness between 1 and 100 micrometers; and

a metallization structure on said first polymer layer and on said first and second contact points, wherein said first contact point is connected to said second contact point through said metallization structure, wherein said metallization structure comprises a titanium-containing layer on said first polymer layer and an electroplated copper layer over said titanium-containing layer.

12. The chip of claim 11, wherein said first polymer layer comprises polyimide.

13. The chip of claim 11, wherein said first polymer layer comprises benzocyclobutene (BCB).

14. The chip of claim 11 further comprising a second polymer layer on said metallization structure.

15. The chip of claim 14, wherein said second polymer layer comprises polyimide.

16. The chip of claim 14, wherein said second polymer layer comprises benzocyclobutene (BCB).

17. The chip of claim 11, wherein said titanium-containing layer comprises a titanium-tungsten alloy.

18. The chip of claim 11, wherein said passivation layer further comprises an oxide layer.

19. The chip of claim 11, wherein said metallization structure on said first polymer layer has a thickness between 1 and 50 micrometers.

20. The chip of claim 11, wherein said metallization structure is further on a sidewall of said first opening and contacts a region of said passivation layer.

21. A chip comprising:

a silicon substrate;

a transistor in or on said silicon substrate;

a metallization structure over said silicon substrate, wherein said metallization structure comprises a first copper layer, a second copper layer over said first copper layer and a copper plug between said first and second copper layers, wherein said second copper layer is connected to said first copper layer through said copper plug;

a dielectric layer over said silicon substrate and between said first and second copper layers, wherein said copper plug is in said dielectric layer;

a passivation layer over said metallization structure and over said dielectric layer, wherein said passivation layer comprises a nitride layer, wherein an opening in said passivation layer is over a contact point of said metallization structure, and said contact point is at a bottom of said opening, wherein said opening has a width between 0.5 and 20 micrometers, wherein said passivation layer has a top surface with a first region and a second region between said first region and a sidewall of said opening;

a polymer layer on said first region, wherein said polymer layer has a thickness between 1 and 100 micrometers; and

a metal interconnect on said contact point, on said sidewall of said opening, on said second region and on a top surface of said polymer layer, wherein said metal interconnect comprises a titanium-containing layer on said contact point, on said sidewall of said opening, on said second region and on said top surface of said polymer layer, and a gold layer over said titanium-containing layer.

22. The chip of claim 21, wherein said polymer layer comprises polyimide.

23. The chip of claim 21, wherein said polymer layer comprises benzocyclobutene (BCB).

24. A chip comprising:

a silicon substrate;

a metallization structure over said silicon substrate, wherein said metallization structure comprises a first copper layer, a second copper layer over said first copper layer and a copper plug between said first and second copper layers, wherein said second copper layer is connected to said first copper layer through said copper plug;

a dielectric layer over said silicon substrate and between said first and second copper layers, wherein said copper plug is in said dielectric layer;

an inorganic layer over said silicon substrate and over said metallization structure, wherein a first opening in said inorganic layer is over a contact point of said metallization structure, and said contact point is at a bottom of said first opening, wherein said first opening has a width between 0.5 and 20 micrometers;

a polymer layer on said inorganic layer, wherein a second opening in said polymer layer is over said contact point;

a first metal layer on said contact point, in said first and second openings and on said polymer layer, wherein said first metal layer comprises a conductive layer and a third copper layer on said conductive layer; and

a second metal layer on said first metal layer, over said contact point and over said polymer layer, wherein said second metal layer comprises gold.

25. The chip of claim 24, wherein said polymer layer comprises polyimide.

26. The chip of claim 24, wherein said conductive layer comprises titanium.