Interface apparatus and methods of testing integrated circuits using the same

• US 7,906,982 B1
• Filed: 02/27/2007
• Issued: 03/15/2011
• Est. Priority Date: 02/28/2006
• Status: Active Grant

• Current Assignee: Infineon Technologies Batam PT (Infineon Technologies AG)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Meade, Richard, Eid, Sherif, Stevens, Lance, Slanina, Miroslav
• Primary Examiner(s): Nguyen, Ha Tran T
• Assistant Examiner(s): ISLA RODAS, RICHARD
• Application Number:
  US11/711,382
• Time in Patent Office: 1,477 Days
• Field of Search: 324754-765, 324/158.1, 703/23
• US Class Current: 324/756.03
• CPC Class Codes: G01R 31/318511 Wafer Test
• CPC Class Codes: G01R 31/31905 Interface with the device under test [DUT], e.g. arrangements between the test head and the DUT, mechanical aspects, fixture
• CPC Class Codes: G01R 31/31926 Routing signals to or from the device under test [DUT], e.g. switch matrix, pin multiplexing

Abstract

An apparatus and method are provided for testing a semiconductor device (DUT). Generally, the apparatus includes an interface board with conductive elements adapted to electrically couple with the DUT and connected to a number of test circuits. Each test circuit resides on one of a number of daughter cards on the interface board, and provides test input signals to and receives output signals from the DUT to generate a result based on a program loaded to the daughter cards before testing begins. The apparatus further includes a controller to drive the interface board and store test results. In one embodiment, the interface board is a load board for back end testing. In another embodiment, the interface board is a probe card for front end testing. Preferably, the apparatus is capable of testing DUTs including memory arrays, logic circuits or both, and the daughter cards are capable of being re-programmed and re-used on different DUTs.

Claims

1. An apparatus for performing electrical tests on at least one device under test (DUT), the apparatus comprising

an interface board provided with a plurality conductive elements adapted to electrically couple with electrical terminals on the DUT and connected to a number of test circuits, each of said test circuits residing on one of a plurality of Field Programmable Gate Array (FPGA) daughter cards on said interface board, and arranged to provide test input signals to said DUT and receive output signals from said DUT to generate a test result based on a program loaded to the FPGA daughter cards before testing begins;

a controller to control said interface board and store therein said test result outputted from said test circuit; and

wherein each of the plurality of FPGA daughter cards include a plurality of FPGAs, and a memory to store the test results, and at least one of the plurality of FPGAs include a logic vector memory (LVM) to test logic circuits in the DUT.

2. An apparatus according to claim 1, wherein the interface board is a load-board, and wherein the plurality conductive elements comprise sockets to receive pins out of a packaged DUT.

3. An apparatus according to claim 1, wherein the interface board is a probe card, and wherein the plurality conductive elements comprise probes to align with and contact electrical pads of the DUT in a die in a semiconductor wafer.

4. An apparatus according to claim 1, wherein the controller comprises a Personal Computer (PC) or a Low-Cost-Tester (LCT).

5. An apparatus according to claim 4, wherein a program is loaded to the memory of at least one of the plurality of FPGA daughter cards before testing begins.

6. An apparatus according to claim 5, wherein the program is loaded directly from the PC or LCT to the memory before testing begins.

7. A method for testing a device under test (DUT) using an apparatus including an interface board with a plurality of Field Programmable Gate Array (FPGA) daughter cards physically and electrically connected thereto, the method comprising:

loading a program to a memory on at least one of the plurality of FPGA daughter cards;

configuring at least one of a number of FPGAs on at least one of the plurality of FPGA daughter cards with the program loaded in the memory before testing begins;

transmitting at least one test signal from a test circuit residing on one of the FPGA daughter cards to at least one electrical terminal on the DUT through a plurality conductive elements on the interface board;

receiving at least one output signal from the DUT to generate a test result; and

storing the test result in the memory.

8. A method according to claim 7, wherein the apparatus comprises a controller to control the interface board.

9. A method according to claim 8, wherein the controller comprises a Personal Computer (PC) or a Low-Cost-Tester (LCT).

10. A method according to claim 7, wherein the interface board is a load-board, and wherein the plurality of conductive elements on the interface board comprise sockets to receive pins out of a packaged DUT.

11. A method according to claim 7, wherein the interface board is a probe card, and wherein the plurality conductive elements on the interface board comprise probes to align with and contact electrical pads of the DUT in a die in a semiconductor wafer.

12. A system comprising:

an interface board including a plurality of conductive elements adapted to electrically couple with terminals on a device under test (DUT); and

a number of Field Programmable Gate Array (FPGA) daughter cards electrically connected to the plurality conductive elements, each of said FPGA daughter cards including a number of FPGAs configured to provide test input signals to terminals on the DUT through the plurality conductive elements and to receive output signals therefrom to generate a test result based on a program loaded to the FPGA daughter cards before testing begins, and a memory electrically connected to the number of FPGAs to store the test results, wherein at least one of the number of FPGAs include a logic vector memory (LVM) to test logic circuits in the DUT.

13. A system according to claim 12, wherein at least one of the number of FPGAs further include an algorithmic pattern generator (APG) to test memory arrays in the DUT.

14. A system according to claim 12, further including a controller electrically coupled to the number of FPGA daughter cards to control the number of FPGAs.

15. A system according to claim 14, wherein the controller is further electrically coupled to the memory to receive from the memory the test results stored therein.

16. A system according to claim 14, wherein the memory is electrically coupled to the controller to store programs from the controller, and is configured to program the number of FPGAs.

17. A system according to claim 15, wherein the memory is configured to store test vectors used to test logic circuits in the DUT.

18. A system according to claim 12, wherein the interface board is a load-board, and wherein the plurality conductive elements comprise sockets to receive pins out of a packaged DUT.

19. A system according to claim 12, wherein the interface board is a probe card, and wherein the plurality conductive elements comprise probes to align with and contact electrical pads of the DUT in a die in a semiconductor wafer.