Programmable logic device having an embedded test logic with secure access control

• US 7,906,983 B2
• Filed: 12/08/2008
• Issued: 03/15/2011
• Est. Priority Date: 12/08/2008
• Status: Active Grant

• Current Assignee: Intuitive Research and Technology Corporation
• Original Assignee: Intuitive Research and Technology Corporation
• Inventors: Fulks, Charles E. III
• Primary Examiner(s): Tan; Vibol
• Assistant Examiner(s): WHITE, DYLAN C
• Application Number:
  US12/330,264
• Publication Number:
  US 20100141295A1
• Time in Patent Office: 827 Days
• Field of Search: 326/8, 326/16, 326 37- 41, 326/47, 713168-191, 380277-285
• US Class Current: 326/8
• CPC Class Codes: G01R 31/318516 Test of programmable logic devices [PLDs]
• CPC Class Codes: H03K 19/17764 for reliability
• CPC Class Codes: H03K 19/17768 for security

Abstract

An improved configuration for a programmable logic device and an improved method for configuration of a programmable logic device are provided. A programmable logic device such as field programmable logic device is configured to include an application logic, an embedded test logic that monitors the application logic, and an access control logic that grants access to an external device to embedded test data provided that an access control requirement is met that is based upon a key stored in a memory and information received from the external device.

Claims

1. A programmable logic device configuration comprising:

an application logic;

an embedded test logic that monitors the application logic to produce embedded test data;

a first memory for storing an access key;

an access control logic that grants an external device access to said embedded test data based upon the stored access key and data received from the external device;

a second memory for storing normal embedded test data values; and

a health monitor logic for monitoring actual values of said embedded test data relative to said normal embedded test data values.

2. The programmable logic device configuration of claim 1, further comprising:

a decryption logic, said decryption logic decrypting encrypted data received from said external device.

3. The programmable logic device configuration of claim 2, wherein said stored access code is used to decrypt said encrypted data.

4. The programmable logic device configuration of claim 1, further comprising:

an encryption logic, said encryption logic encrypting said embedded test data.

5. The programmable logic device configuration of claim 4, wherein said stored access code is used to encrypt said embedded test data.

6. The programmable logic device configuration of claim 1, wherein said external device interfaces with said programmable logic device using at least one of a Joint Test Action Group port, a configuration access port, or an input/output port.

7. The programmable logic device configuration of claim 1, further comprising:

a Joint Test Action Group logic.

8. The programmable logic device configuration of claim 7, wherein said access control logic provides an access control layer between said Joint Test Action Group logic and said embedded test logic.

9. The programmable logic device configuration of claim 1, wherein said health monitor logic provides a warning to said external device when said actual values of said embedded test data are determined to be unacceptable when compared to said normal embedded test data values.

10. A method for programming a configuration of a programmable logic device comprising the steps of:

creating on the programmable logic device an application logic;

creating on the programmable logic device an embedded test logic that monitors the application logic to produce embedded test data; and

creating on the programmable logic device an access control logic that grants an external device access to said embedded test data based upon an access key stored in a memory and data received from the external device; and

creating on the programmable logic device a health monitor logic for monitoring actual values of said embedded test data relative to normal embedded test data values stored in a second memory.

11. The method of claim 10, further comprising the step of:

creating on the programmable logic device a decryption logic, said decryption logic decrypting encrypted data received from said external device.

12. The method of claim 11, wherein said decryption logic uses said stored access code to decrypt said encrypted data.

13. The method of claim 10, further comprising:

creating on the programmable logic device an encryption logic, said encryption logic encrypting said embedded test data.

14. The method of claim 13, wherein said encryption logic uses said stored access code to encrypt said embedded test data.

15. The method of claim 10, further comprising:

creating on the programmable logic device a Joint Test Action Group logic.

16. The method of claim 15, wherein said access control logic provides an access control layer between said Joint Test Action Group logic and said embedded test logic.

17. The method of claim 10, wherein said health monitor logic provides a warning to said external device when said actual values of said embedded test data are determined to be unacceptable when compared to said normal embedded test data values.

18. The method of claim 17, further comprising:

creating on the programmable logic device an encryption logic, said encryption logic encrypting said warning.