Display controller blinking mode circuitry for LCD panel of twisted nematic type
First Claim
1. A discrete display panel controller comprising:
- a first set of registers configured to hold data to be displayed;
first logic circuitry connected to said first set of registers, said first logic circuitry configured to receive said data from said first set of registers, generate signal waveforms to be received by a discrete display panel according to said data, and provide said signal waveforms to said discrete display panel;
second logic circuitry connected to said first logic circuitry, said second logic circuitry configured to generate timing signals for timing said first logic circuitry; and
a resistor ladder connected to said second logic circuitry, said resistor ladder configured to generate intermediate voltages to drive said discrete display panel, and configured to receive said timing signals from said second logic circuitry,wherein said controller is configured to automatically and periodically disable said resistor ladder according to one of said timing signals, while preventing said signal waveforms from arriving at said discrete display panel by gating and clearing said signal waveforms after being generated by the first logic circuitry.
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Accused Products
Abstract
A display controller for providing signals to a discrete display panel unit comprising: a set of registers configured to hold data to be displayed; a first logic circuitry connected to the set of registers and configured to receive the data from the set of registers, generate the signal waveforms required by the display panel according to the data, and provide the signal waveforms to the display panel; a second logic circuitry connected to the first logic circuitry, the second logic circuitry configured to generate timing signals for timing the first logic circuitry providing the waveforms to the display panel; and a resistor ladder connected to the second logic circuitry, the resistor ladder configured to generate intermediate voltages required to drive the display panel, and configured to receive the timing signals, wherein the controller is configured to automatically and periodically disable the resistor ladder according to one of the timing signals.
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Citations
21 Claims
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1. A discrete display panel controller comprising:
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a first set of registers configured to hold data to be displayed; first logic circuitry connected to said first set of registers, said first logic circuitry configured to receive said data from said first set of registers, generate signal waveforms to be received by a discrete display panel according to said data, and provide said signal waveforms to said discrete display panel; second logic circuitry connected to said first logic circuitry, said second logic circuitry configured to generate timing signals for timing said first logic circuitry; and a resistor ladder connected to said second logic circuitry, said resistor ladder configured to generate intermediate voltages to drive said discrete display panel, and configured to receive said timing signals from said second logic circuitry, wherein said controller is configured to automatically and periodically disable said resistor ladder according to one of said timing signals, while preventing said signal waveforms from arriving at said discrete display panel by gating and clearing said signal waveforms after being generated by the first logic circuitry. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A method comprising:
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holding data in a first set of registers included in a display controller, the data to be displayed on a discrete display panel; using second logic circuitry in the controller to generate timing signals alternating between different values, and to transmit at least a first one of the timing signals to first logic circuitry in the controller and a resistor ladder in the controller; transmitting said held data from said first set of registers to said first logic circuitry; receiving said at least the first one of said timing signals at said first logic circuitry from said second logic circuitry, and receiving said data from said first set of registers; generating signal waveforms by said first logic circuitry according to said received data; transmitting said signal waveforms from said first logic circuitry to said discrete display panel; periodically preventing the arrival of said signal waveforms at said discrete display panel by gating and using said controller to clear said signal waveforms after being generated by said first logic circuitry; receiving at least a second one of the timing signals at said resistor ladder from said second logic circuitry; not generating any intermediate voltages by said resistor ladder at some time during the preventing and when said received at least the second one of the timing signals has a first value; and generating intermediate voltages by said resistor ladder and transmitting said generated intermediate voltages from said resistor ladder to said discrete display panel when said received at least the second one of the timing signals has a second value different from said first value. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19, 20, 21)
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Specification