Display controller blinking mode circuitry for LCD panel of twisted nematic type

• US 7,907,110 B2
• Filed: 04/04/2007
• Issued: 03/15/2011
• Est. Priority Date: 04/04/2007
• Status: Active Grant

• Current Assignee: Atmel Corporation (Microchip Technology Incorporated)
• Original Assignee: Atmel Corporation (Microchip Technology Incorporated)
• Inventors: Vergnes, Alain, Alingry, Jerome, Younes, Sebastien
• Primary Examiner(s): Shalwala; Bipin
• Assistant Examiner(s): Spar; Ilana
• Application Number:
  US11/696,574
• Publication Number:
  US 20080246746A1
• Time in Patent Office: 1,441 Days
• Field of Search: 345/204, 345/690, 345/691, 345211-213, 345 87-104
• US Class Current: 345/98
• CPC Class Codes: G09G 2310/0278 Details of driving circuits arranged to drive both scan and data electrodes
• CPC Class Codes: G09G 2310/061 for resetting or blanking
• CPC Class Codes: G09G 2330/021 Power management, e.g. power saving
• CPC Class Codes: G09G 2360/18 Use of a frame buffer in a display terminal, inclusive of the display panel
• CPC Class Codes: G09G 3/3611 Control of matrices with row and column drivers
• CPC Class Codes: G09G 3/3614 Control of polarity reversal in general
• CPC Class Codes: G09G 3/3622 using a passive matrix G09G3/3674 - G09G3/3696 take precedence
• CPC Class Codes: G09G 3/3696 Generation of voltages supplied to electrode drivers

Abstract

A display controller for providing signals to a discrete display panel unit comprising: a set of registers configured to hold data to be displayed; a first logic circuitry connected to the set of registers and configured to receive the data from the set of registers, generate the signal waveforms required by the display panel according to the data, and provide the signal waveforms to the display panel; a second logic circuitry connected to the first logic circuitry, the second logic circuitry configured to generate timing signals for timing the first logic circuitry providing the waveforms to the display panel; and a resistor ladder connected to the second logic circuitry, the resistor ladder configured to generate intermediate voltages required to drive the display panel, and configured to receive the timing signals, wherein the controller is configured to automatically and periodically disable the resistor ladder according to one of the timing signals.

Claims

1. A discrete display panel controller comprising:

a first set of registers configured to hold data to be displayed;

first logic circuitry connected to said first set of registers, said first logic circuitry configured to receive said data from said first set of registers, generate signal waveforms to be received by a discrete display panel according to said data, and provide said signal waveforms to said discrete display panel;

second logic circuitry connected to said first logic circuitry, said second logic circuitry configured to generate timing signals for timing said first logic circuitry; and

a resistor ladder connected to said second logic circuitry, said resistor ladder configured to generate intermediate voltages to drive said discrete display panel, and configured to receive said timing signals from said second logic circuitry,

wherein said controller is configured to automatically and periodically disable said resistor ladder according to one of said timing signals, while preventing said signal waveforms from arriving at said discrete display panel by gating and clearing said signal waveforms after being generated by the first logic circuitry.

2. The controller of claim 1, further comprising a logic gate to provide the gating and connected to said first logic circuitry and said second logic circuitry, said logic gate configured to receive said signal waveforms from said first logic circuitry, receive said timing signals from said second logic circuitry, and provide said received signal waveforms to said discrete display panel.

3. The controller of claim 2, wherein said logic gate is an AND gate.

4. The controller of claim 1, further comprising a transistor connected between said second logic circuitry and said resistor ladder, wherein said transistor is configured to receive said timing signals and disable said resistor ladder according to one of said timing signals.

5. The controller of claim 1, wherein said controller is configured to clear said signal waveforms provided to said discrete display panel for a period of time corresponding approximately to the period of time said resistor ladder is disabled.

6. The controller of claim 1, wherein the discrete display panel is a multiple common terminal twisted nematic liquid crystal display panel.

7. The controller of claim 1, wherein said controller is connected in a system using a microprocessor, said microprocessor configured to access said first set of registers.

8. The controller of claim 1, wherein said controller is disposed in a microcontroller integrated circuit.

9. The controller of claim 8, wherein said microcontroller integrated circuit comprises.

a first set of input terminals configured to supply power to said display controller;

and

a second set of input terminals configured to supply power to said microprocessor, wherein said first set of input terminals and said second set of input terminals are disconnected within said microcontroller integrated circuit.

10. The controller of claim 1, further comprising a second set of registers connected to said second logic circuitry and between said first set of registers and said first logic circuitry, said second set of registers configured to receive timing signals from said second logic circuitry and load said data from said first set of registers periodically based on said received timing signals.

11. The controller of claim 1, further comprising a multiplexer connected to said second logic circuitry and between said first set of registers and said first logic circuitry, said multiplexer configured to receive at least some of the timing signals from said second logic circuitry, receive said data from said first set of registers, and provide said data to said first logic circuitry based on said received timing signals.

12. A method comprising:

holding data in a first set of registers included in a display controller, the data to be displayed on a discrete display panel;

using second logic circuitry in the controller to generate timing signals alternating between different values, and to transmit at least a first one of the timing signals to first logic circuitry in the controller and a resistor ladder in the controller;

transmitting said held data from said first set of registers to said first logic circuitry;

receiving said at least the first one of said timing signals at said first logic circuitry from said second logic circuitry, and receiving said data from said first set of registers;

generating signal waveforms by said first logic circuitry according to said received data;

transmitting said signal waveforms from said first logic circuitry to said discrete display panel;

periodically preventing the arrival of said signal waveforms at said discrete display panel by gating and using said controller to clear said signal waveforms after being generated by said first logic circuitry;

receiving at least a second one of the timing signals at said resistor ladder from said second logic circuitry;

not generating any intermediate voltages by said resistor ladder at some time during the preventing and when said received at least the second one of the timing signals has a first value; and

generating intermediate voltages by said resistor ladder and transmitting said generated intermediate voltages from said resistor ladder to said discrete display panel when said received at least the second one of the timing signals has a second value different from said first value.

13. The method of claim 12, wherein said display controller further comprises a logic gate connected to said first logic circuitry and said second logic circuitry, and said method further comprises:

receiving a signal waveform from said first logic circuitry at said logic gate;

receiving a timing signal from said second logic circuitry; and

transmitting said received signal waveform to said discrete display panel when the arrival of said received signal waveform is not being prevented.

14. The method of claim 13, wherein receiving the signal waveform further comprises:

receiving the signal waveform at said logic gate as an AND gate.

15. The method of claim 12, wherein said display controller further comprises a transistor connected between said second logic circuitry and said resistor ladder, and said method further comprises:

receiving said timing signal from said second logic circuitry at said transistor; and

disabling said resistor ladder by said transistor according to said received timing signal.

16. The method of claim 12, further comprising:

clearing, using said controller, said signal waveforms provided to said discrete display panel for a period of time corresponding approximately to the period of time said resistor ladder is not generating any intermediate voltages.

17. The method of claim 12, wherein the data is to be displayed on the discrete display panel comprising a multiple common terminal twisted nematic liquid crystal display panel.

18. The method of claim 12, wherein said controller is connected in a system using a microprocessor, comprising:

accessing said first set of registers with said microprocessor.

19. The method of claim 12, comprising:

periodically clearing said signal waveforms using said controller disposed in a microcontroller integrated circuit.

20. The method of claim 12, wherein said display controller further comprises a second set of registers connected to said second logic circuitry and between said first set of registers and said first logic circuitry, wherein said method further comprises:

receiving timing signals from said second logic circuitry at said second set of registers; and

loading said held data by said second set of registers from said first set of registers periodically based on said received timing signals.

21. The method of claim 12, wherein said display controller further comprises a multiplexer connected to said second logic circuitry and between said first set of registers and said first logic circuitry, said method comprising:

receiving timing signals by said multiplexer from said second logic circuitry;

receiving said held data by said multiplexer from said first set of registers; and

transmitting said data by said multiplexer to said first logic circuitry based on said received timing signals.