Semiconductor apparatus having a large-size bus connection

• US 7,907,434 B2
• Filed: 11/26/2007
• Issued: 03/15/2011
• Est. Priority Date: 11/29/2000
• Status: Expired due to Fees

• Current Assignee: Socionext Inc.
• Original Assignee: Fujitsu Semiconductor Limited (Fujitsu Limited)
• Inventors: Sato, Yasuharu, Suzuki, Takaaki, Aikawa, Tadao, Matsuzaki, Yasurou, Yamazaki, Masafumi
• Primary Examiner(s): Pham; Ly D
• Application Number:
  US11/984,932
• Publication Number:
  US 20080142847A1
• Time in Patent Office: 1,205 Days
• Field of Search: 365/63, 257/211, 257/266, 257/635, 257/758
• US Class Current: 365/63
• CPC Class Codes: G11C 5/00 Details of stores covered by group G11C11/00
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: G11C 5/06 Arrangements for interconnecting storage elements electrically, e.g. by wiring
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: H01L 2224/023 Redistribution layers [RDL] for bonding areas
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06562 at least one device in the stack being rotated or offset
• CPC Class Codes: H01L 25/0652 the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0001 Technical content checked by a classifier
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/13091 Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H04L 12/40 Bus networks
• CPC Class Codes: H04L 12/4625 Single bridge functionality, e.g. connection of two networks over a single bridge
• CPC Class Codes: H10B 41/00 Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates

Abstract

In a semiconductor apparatus of the present invention, a plurality of circuit components are provided. A first bus interconnects the circuit components. A second bus interconnects the circuit components. A switching unit outputs a select signal that causes each circuit component to select one of the first bus and the second bus when transmitting a signal from one of the circuit components to another. The second bus has a size larger than a size of the first bus.

Claims

1. A semiconductor apparatus having circuit components, comprising:

a first bus interconnecting the circuit components;

a second bus interconnecting the circuit components; and

a switching unit outputting a select signal that causes each circuit component to select one of the first bus and the second bus when transmitting a signal from one of the circuit components to another,

the second bus having a size larger than a size of the first bus,

wherein the first bus is provided for transmission of the signal between the circuit components before formation of the second bus, and, when the semiconductor apparatus operates before the formation of the second bus, the signal is transmitted on the first bus from one of the circuit components to another.

3. The semiconductor apparatus according to claim 1, wherein the first bus and the second bus are provided to transmit a same signal from one of the circuit components to another.

4. The semiconductor apparatus according to claim 1, wherein the first bus and the second bus are provided to transmit at least one of an address signal, a data signal, a control signal and a clock signal between the circuit components.

6. The semiconductor apparatus according to claim 1, wherein the switching unit is provided to establish electrical connection between the circuit components by only the selected one of the first bus and the second bus.

7. The semiconductor apparatus according to claim 1, wherein the switching unit is provided with a programmable device.

8. The semiconductor apparatus according to claim 1, wherein the second bus includes signal line portions having a substantially equal length.

2. A semiconductor apparatus having circuit components, comprising:

a first bus interconnecting the circuit components;

a second bus interconnecting the circuit components; and

a switching unit outputting a select signal that causes each circuit component to select one of the first bus and the second bus when transmitting a signal from one of the circuit components to another,

the switching unit being configured such that the first bus is selected only when a wafer test is conducted before formation of the second bus, and the second bus is selected at any time the semiconductor apparatus operates after the wafer test is conducted.

5. A semiconductor apparatus having circuit components, comprising:

a first bus interconnecting the circuit components;

a second bus interconnecting the circuit components; and

a switching unit outputting a select signal that causes each circuit component to select one of the first bus and the second bus when transmitting a signal from one of the circuit components to another,

the second bus having a size larger than a size of the first bus,

wherein the switching unit is configured such that the second bus is always selected when the semiconductor apparatus operates after the formation of the second bus in the semiconductor apparatus.

9. A semiconductor apparatus having circuit components, comprising:

a first wiring layer provided on a chip and including a number M of first electrodes, the M first electrodes being connected to the circuit components via a first bus; and

a second wiring layer provided above the first wiring layer and including a number N of second electrodes, the N second electrodes being connected to the circuit components via a second bus, the second bus having a size larger than a size of the first bus,

wherein the semiconductor apparatus is configured such that a clock signal is received at each of the first electrodes and the second electrodes and the conditions M>

N.box-solid.1 are met,

wherein the circuit components includes respective receiver units each of which is connected to one of the M first electrodes, and, when a select signal is set at a first level, the clock signal received at each first electrode is transmitted through the first wiring layer to corresponding one of the circuit components, and, when the select signal is set at a second level, the clock signal received at each second electrode is transmitted through the second wiring layer to corresponding one of the circuit components.