Methods and apparatus for implementing bit-by-bit erase of a flash memory device

• US 7,907,450 B2
• Filed: 10/13/2006
• Issued: 03/15/2011
• Est. Priority Date: 05/08/2006
• Status: Active Grant

• Current Assignee: Macronix International Co., Ltd.
• Original Assignee: Macronix International Co., Ltd.
• Inventors: Lai, Erh Kun, Lue, Hang-Ting
• Primary Examiner(s): Hoang; Huan
• Assistant Examiner(s): Hidalgo; Fernando N
• Application Number:
  US11/549,502
• Publication Number:
  US 20070258291A1
• Time in Patent Office: 1,614 Days
• Field of Search: 365/185.18, 365/185.17, 365/185.28, 365/185.29, 365/185.33, 365/176, 365/161, 365/185.11, 365/185.05, 257/296
• US Class Current: 365/185.18
• CPC Class Codes: G11C 16/0466 comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/12 Programming voltage switching circuits
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H10B 43/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A NAND memory device is constructed using Silicon On Insulator (SOI) techniques. In particular, Thin Film Transistor (TFT) techniques can be used to fabricate the NAND Flash memory device. In both SOI and TFT structures, the body, or well, is isolated. This can be used to enable a bit-by-bit programming and erasing of individual cells and allows tight control of the threshold voltage, which can enable MLC operation.

Claims

1. A method for operating an array of charge storage memory cells arranged in a NAND configuration including a plurality of NAND cells on semiconductor lines and a plurality of word lines coupled in parallel to the NAND cells, the plurality of semiconductor lines on an insulating layer and isolated from adjacent semiconductor lines of the NAND cells by isolation structures on the insulating layer, memory cells in the array including charge trapping structures overlying channel regions separated by source and drain regions in a corresponding semiconductor line, the method comprising:

changing a data value stored in a target memory cell in a first NAND cell in the array, said changing comprising;

applying a first bit line voltage to the semiconductor line of the first NAND cell;

applying a first word line voltage to a corresponding word line of the target memory cell, the first word line voltage and the first bit line voltage differing by an amount sufficient to change the data value stored in the target memory cell; and

applying a second word line voltage to corresponding word lines of the remaining memory cells in the first NAND cell, thereby coupling the first bit line voltage to the channel region of the target memory cell, the first bit line voltage and the second word line voltage differing by an amount sufficient to maintain respective data values stored in the remaining memory cells of the first NAND cell.

2. The method of claim 1, wherein the changing the data value stored in the target memory cell comprises increasing a threshold voltage of the target memory cell.

3. The method of claim 2, wherein:

the difference between the first word line voltage and the first bit line voltage is in the range of 14 to 20 Volts; and

the difference between the second word voltage and the first bit line voltage is in the range of 6 to 12 Volts.

4. The method of claim 3, wherein:

the first word line voltage is in the range of 14 to 20 Volts;

the second word line voltage is in the range of 6 to 12 Volts;

the first bit line voltage is 0 Volts.

5. The method of claim 1, wherein the changing the data value stored in the target memory cell comprises decreasing a threshold voltage of the target memory cell.

6. The method of claim 5, wherein:

the difference between the first word line voltage and the first bit line voltage is in the range of −

15 to −

21 Volts; and

the difference between the second word line voltage and the first bit line voltage is in the range of −

1 to 5 Volts.

7. The method of claim 6, wherein:

the first word line voltage is in the range of −

7 to −

13 Volts;

the second word line voltage is in the range of 7 to 13 Volts;

the first bit line voltage is 8 Volts.

8. The method of claim 1, wherein the charge trapping structure of memory cells in the array comprise:

a first oxide layer on a corresponding semiconductor line;

a nitride charge trapping layer overlying the first oxide layer; and

a second oxide layer overlying the nitride charge trapping layer, wherein the corresponding word line is overlying the second oxide layer.

9. The method of claim 1, wherein the charge trapping structure of memory cells in the array comprise:

a first oxide layer on a corresponding semiconductor line;

a nitride charge trapping layer on the first oxide layer; and

a second oxide layer on the nitride charge trapping layer, wherein the corresponding word line is on the second oxide layer.

10. The method of claim 1, wherein the charge trapping structure of memory cells in the array comprise:

a first oxide layer on a corresponding semiconductor line;

a first nitride layer on the first oxide layer;

a second oxide layer on the first oxide layer;

a second nitride layer on the second oxide layer; and

a third oxide layer on the second nitride layer, wherein the corresponding word line is on the third oxide layer.

11. The method of claim 10, wherein the first nitride layer is a charge trapping layer.

12. The method of claim 10, wherein the second nitride layer is a charge trapping layer.

13. The method of claim 1, wherein the array of charge storage memory cells are arranged in a 3-dimensional NAND configuration and further include:

a second plurality of NAND cell semiconductor lines overlying the plurality of word lines; and

a second plurality of word lines overlying the second plurality of NAND cell semiconductor lines.

14. The method of claim 1, wherein the array of charge storage memory cells are manufactured using a thin-film-transistor fabrication technique.

15. The method of claim 1, further comprising applying a second bit line voltage to the semiconductor line of a second NAND cell semiconductor line, the first word line voltage and the second bit line voltage differing by an amount sufficient to maintain a data value stored in a memory cell in the second NAND cell coupled to the corresponding word line of the target memory cell.

16. The method of claim 15, further comprising changing a data value stored in a second target memory cell in the second NAND cell while changing the data value stored in the target cell in the first NAND cell, the second target cell coupled to the same word line as one of the remaining memory cells in the first NAND cell, and the second bit line voltage and the second word line voltage differing by an amount sufficient to change the data value stored in the second target cell.

17. The method of claim 16, wherein:

the changing the data value stored in the target memory cell comprises increasing the threshold voltage of the target memory cell; and

the changing the data value stored in the second target memory cell comprises decreasing the threshold voltage of the second target memory cell.

18. The method of claim 16, wherein:

the changing the data value stored in the target memory cell comprises decreasing the threshold voltage of the target memory cell; and

the changing the data value stored in the second target memory cell comprises increasing the threshold voltage of the second target memory cell.

19. A method for operating an array of charge storage memory cells arranged in a NAND configuration including a plurality of NAND cells on semiconductor lines and a plurality of word lines coupled in parallel to the NAND cells, the plurality of semiconductor lines on an insulating layer and isolated from adjacent semiconductor lines of the NAND cells, memory cells in the array including charge trapping structures overlying channel regions separated by source and drain regions in a corresponding semiconductor line, the method comprising:

changing a data value stored in a target memory cell in a first NAND cell in the array, said changing comprising;

applying a first bit line voltage to the semiconductor line of the first NAND cell;

applying a first word line voltage to a corresponding word line of the target memory cell, the first word line voltage and the first bit line voltage differing by an amount sufficient to change the data value stored in the target memory cell; and

applying a second word line voltage to corresponding word lines of the remaining memory cells in the first NAND cell, thereby coupling the first bit line voltage to the channel region of the target memory cell, the first bit line voltage and the second word line voltage differing by an amount sufficient to maintain respective data values stored in the remaining memory cells of the first NAND cell; and

applying a second bit line voltage to the semiconductor line of a second NAND cell semiconductor line, the first word line voltage and the second bit line voltage differing by an amount sufficient to maintain a data value stored in a memory cell in the second NAND cell coupled to the corresponding word line of the target memory cell, wherein;

changing the data value stored in the target memory cell comprises increasing the threshold voltage of the target memory cell by at least 3 Volts; and

maintaining the data value stored in the memory cell in the second NAND cell comprises changing a threshold voltage of the memory cell by less than 0.5 Volts.

20. A method for operating an array of charge storage memory cells arranged in a NAND configuration including a plurality of NAND cells on semiconductor lines and a plurality of word lines coupled in parallel to the NAND cells, the plurality of semiconductor lines on an insulating layer and isolated from adjacent semiconductor lines of the NAND cells, memory cells in the array including charge trapping structures overlying channel regions separated by source and drain regions in a corresponding semiconductor line, the method comprising:

changing a data value stored in a target memory cell in a first NAND cell in the array, said changing comprising;

applying a first bit line voltage to the semiconductor line of the first NAND cell;

applying a first word line voltage to a corresponding word line of the target memory cell, the first word line voltage and the first bit line voltage differing by an amount sufficient to change the data value stored in the target memory cell; and

applying a second word line voltage to corresponding word lines of the remaining memory cells in the first NAND cell, thereby coupling the first bit line voltage to the channel region of the target memory cell, the first bit line voltage and the second word line voltage differing by an amount sufficient to maintain respective data values stored in the remaining memory cells of the first NAND cell; and

applying a second bit line voltage to the semiconductor line of a second NAND cell semiconductor line, the first word line voltage and the second bit line voltage differing by an amount sufficient to maintain a data value stored in a memory cell in the second NAND cell coupled to the corresponding word line of the target memory cell, wherein;

changing the data value stored in the target memory cell comprises decreasing the threshold voltage of the target memory cell by at least 1 Volt; and

maintaining the data value stored in the memory cell in the second NAND cell comprises changing a threshold voltage of the memory cell by less than 0.5 Volts.

21. A method for operating an array of charge storage memory cells arranged in a NAND configuration including a plurality of NAND cells on semiconductor lines and a plurality of word lines coupled in parallel to the NAND cells, the plurality of semiconductor lines on an insulating layer and isolated from adjacent semiconductor lines of the NAND cells, memory cells in the array including charge trapping structures overlying channel regions separated by source and drain regions in a corresponding semiconductor line, the method comprising:

changing a data value stored in a target memory cell in a first NAND cell in the array by decreasing a threshold voltage of the target memory cell, said changing comprising;

applying a first bit line voltage to the semiconductor line of the first NAND cell;

applying a first word line voltage to a corresponding word line of the target memory cell, the first word line voltage and the first bit line voltage differing by an amount sufficient to change the data value stored in the target memory cell; and

applying a second word line voltage to corresponding word lines of the remaining memory cells in the first NAND cell, thereby coupling the first bit line voltage to the channel region of the target memory cell, the first bit line voltage and the second word line voltage differing by an amount sufficient to maintain respective data values stored in the remaining memory cells of the first NAND cell.