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RSSI-based powerdown apparatus and method for a wireless communications system

  • US 7,907,555 B1
  • Filed: 11/26/2007
  • Issued: 03/15/2011
  • Est. Priority Date: 11/26/2007
  • Status: Active Grant
First Claim
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1. A signal processor for a wireless receiver, the signal processor having:

  • an analog processor including;

    a first amplifier coupled to an antenna receiving wireless signals;

    a mixer coupled to said first amplifier and generating a quadrature baseband signal;

    a second amplifier coupled to said quadrature baseband signal and having a second amplifier output;

    an IQ analog to digital converter (IQ ADC) coupled to said second amplifier output, said IQ ADC having a powerdown state and an operational state;

    a baseband processor coupled to said analog to digital converter outputs and generating a packet detect signal including an end of packet averaging signal;

    a received signal strength indicator (RSSI) which varies with the strength of said wireless signals;

    a threshold generator forming a first threshold from said RSSI signal by averaging said RSSI signal when said end of packet averaging signal is active, thereby forming a second threshold formed by increasing said first threshold by a threshold increment;

    whereby said IQ ADC operates at said operational state when said RSSI exceeds said second threshold and said IQ ADC operates at said powerdown state at other times.

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