RFID tags having a rectifier circuit including a dual-terminal rectifier device

• US 7,907,899 B1
• Filed: 07/10/2006
• Issued: 03/15/2011
• Est. Priority Date: 07/13/2005
• Status: Active Grant

• Current Assignee: Impinj, Inc.
• Original Assignee: Impinj, Inc.
• Inventors: Oliver, Ronald A.
• Primary Examiner(s): LE, NHAN T
• Application Number:
  US11/484,523
• Time in Patent Office: 1,709 Days
• Field of Search: 455/41.2, 455/333, 455/334, 4553431-3434, 340/572.1, 340/572.5, 340/572.7, 340/825.62, 340/825.69, 327/389, 327/343, 327/534, 327/535
• US Class Current: 455/41.2
• CPC Class Codes: G06K 19/0707 the arrangement being capable of collecting energy from external energy sources, e.g. thermocouples, vibration, electromagnetic radiation G06K19/0702 takes precedence
• CPC Class Codes: G06K 19/0723 the record carrier comprising an arrangement for non-contact communication, e.g. wireless communication circuits on transponder cards, non-contact smart cards or RFIDs

Abstract

Apparatus and method for generating a rectified output signal in a RFID tag from first and second alternating signals. A dual-terminal rectifier device has first and second input terminals to which the first and second alternating signals are applied, and further has a gate configured to form a conductive channel to electrically couple the first and second input terminals to the output terminal in response to a gate voltage. The dual-terminal rectifier device is configured to rectify a combination of the alternating input signals applied to the input terminals of the semiconductor device to generate a rectified output signal at an output terminal.

Claims

1. A circuit for a Radio Frequency Identification tag, comprising:

first and second antenna input signal nodes configured to receive a first and second alternating input signal, respectively; and

a power management unit having a plurality of successive stages, each stage coupled to the first and second antenna input nodes, at least one of the stages including;

a dual-terminal rectifier device having first and second input terminals coupled to first and second antenna input signal nodes, respectively, the dual-terminal rectifier further having an output terminal and a gate, the gate configured to form a conductive channel that electrically couples the first and second input terminals to the output terminal in response to a gate voltage, the dual-terminal rectifier device configured to rectify a combination of the alternating input signals applied to the input terminals of the semiconductor device to generate a rectified output signal at the output terminal.

2. The circuit of claim 1 wherein the dual-terminal rectifier device comprises a dual-source field effect transistor.

3. The circuit of claim 2, further comprising:

a bias circuit coupled to the dual-source field effect transistor and configured to provide a bias voltage to the gate.

4. The circuit of claim 1, further comprising:

a dual-terminal rectifier input stage having an input and further having first and second output nodes coupled to the first and second input terminals of the dual-terminal rectifier device, the dual-terminal rectifier input stage configured to provide first and second rectified output signals at the first and second output nodes in response to an input signal applied to the input.

5. The circuit of claim 4 wherein the dual-terminal rectifier input stage comprises a dual-output diode.

6. The circuit of claim 4 wherein the dual-terminal rectifier input stage comprises:

a first diode having an output coupled to the first input terminal of the dual-terminal rectifier device and operable to provide a rectified output signal thereto; and

a second diode having an output coupled to the second input terminal of the dual-terminal rectifier device and operable to provide a rectified output signal thereto.

7. The circuit of claim 4 wherein the dual-terminal rectifier input stage comprises a dual-source field effect transistor having a first source coupled to the first input terminal of the dual-terminal rectifier device and further having a second source coupled to the second input terminal of the dual-terminal rectifier device.

8. The circuit of claim 7 wherein the dual-source field effect transistor has a gate and the RFID circuit further comprises an input biasing circuit coupled to the dual-source field effect transistor and configured to provide a bias voltage to the gate.

9. The circuit of claim 1, further comprising:

a first reference transistor having a gate terminal and a source coupled to the gate of the dual-terminal rectifier device, and further having a drain terminal coupled to the output of the dual-terminal rectifier device;

a first current source coupled to the source of the first reference transistor and configured to provide a first bias current to the source of the first reference transistor;

a second reference transistor having a gate terminal and a drain coupled to a gate of the dual-terminal rectifier input stage, and further having a source terminal coupled to the input of the dual-terminal rectifier input stage; and

a second current source coupled to the drain of the second reference transistor and configured to provide a second bias current to the source of the first second reference transistor.

10. The circuit of claim 1, further comprising:

a first reference transistor having a gate terminal and a source coupled to the gate of the dual-terminal rectifier device, and further having a drain terminal coupled to the output of the dual-terminal rectifier device;

a second reference transistor having a gate terminal and a drain coupled to a gate of the dual-terminal rectifier input stage, and further having a source terminal coupled to the input of the dual-terminal rectifier input stage; and

a current source coupled to the source of the first reference transistor and to the drain of the second reference transistor and configured to provide a bias current.

11. The circuit of claim 1, further comprising:

a first bias circuit coupled to the gate of the dual-terminal rectifier device and configured to provide a gate bias thereto; and

a second bias circuit coupled to a gate of a dual-terminal rectifier input stage and configured to provide a gate bias thereto.

12. A Radio Frequency Identification tag, comprising:

an antenna; and

an integrated circuit (IC) coupled to the antenna, comprising;

first and second antenna input signal nodes coupled to the antenna and configured to receive a first and second alternating input signal, respectively; and

a power management unit having a plurality of successive stages, each stage coupled to the first and second antenna input nodes, at least one of the stages including;

a dual-terminal rectifier device having first and second input terminals coupled to first and second antenna input signal nodes, respectively, the dual-terminal rectifier further having an output terminal and a gate, the gate configured to form a conductive channel that electrically couples the first and second input terminals to the output terminal in response to a gate voltage, the dual-terminal rectifier device configured to rectify a combination of the alternating input signals applied to the input terminals of the semiconductor device to generate a rectified output signal at the output terminal.

13. The tag of claim 12 in which the dual-terminal rectifier device comprises a dual-source field effect transistor.

14. The tag of claim 13 in which the IC further comprises:

a bias circuit coupled to the dual-source field effect transistor and configured to provide a bias voltage to the gate.

15. The tag of claim 12 in which the IC further comprises:

a dual-terminal rectifier input stage having an input and further having first and second output nodes coupled to the first and second input terminals of the dual-terminal rectifier device, the dual-terminal rectifier input stage configured to provide first and second rectified output signals at the first and second output nodes in response to an input signal applied to the input.

16. The tag of claim 15 in which the dual-terminal rectifier input stage comprises a dual-output diode.

17. The tag of claim 15 in which the dual-terminal rectifier input stage comprises:

a first diode having an output coupled to the first input terminal of the dual-terminal rectifier device and operable to provide a rectified output signal thereto; and

a second diode having an output coupled to the second input terminal of the dual-terminal rectifier device and operable to provide a rectified output signal thereto.

18. The tag of claim 15 in which the dual-terminal rectifier input stage comprises a dual-source field effect transistor having a first source coupled to the first input terminal of the dual-terminal rectifier device and further having a second source coupled to the second input terminal of the dual-terminal rectifier device.

19. The tag of claim 18 in which the dual-source field effect transistor has a gate and the RFID circuit further comprises an input biasing circuit coupled to the dual-source field effect transistor and configured to provide a bias voltage to the gate.

20. The tag of claim 12 in which the IC further comprises:

a first reference transistor having a gate terminal and a source coupled to the gate of the dual-terminal rectifier device, and further having a drain terminal coupled to the output of the dual-terminal rectifier device;

a first current source coupled to the source of the first reference transistor and configured to provide a first bias current to the source of the first reference transistor;

a second reference transistor having a gate terminal and a drain coupled to a gate of the dual-terminal rectifier input stage, and further having a source terminal coupled to the input of the dual-terminal rectifier input stage; and

a second current source coupled to the drain of the second reference transistor and configured to provide a second bias current to the source of the first reference transistor.

21. The tag of claim 12 in which the IC further comprises:

a first reference transistor having a gate terminal and a source coupled to the gate of the dual-terminal rectifier device, and further having a drain terminal coupled to the output of the dual-terminal rectifier device;

a second reference transistor having a gate terminal and a drain coupled to a gate of the dual-terminal rectifier input stage, and further having a source terminal coupled to the input of the dual-terminal rectifier input stage; and

a current source coupled to the source of the first reference transistor and to the drain of the second reference transistor and configured to provide a bias current.

22. The tag of claim 12 in which the IC further comprises:

a first bias circuit coupled to the gate of the dual-terminal rectifier device and configured to provide a gate bias thereto; and

a second bias circuit coupled to a gate of a dual-terminal rectifier input stage and configured to provide a gate bias thereto.