Apparatus and method of page program operation for memory devices with mirror back-up of data

• US 7,908,429 B2
• Filed: 07/08/2010
• Issued: 03/15/2011
• Est. Priority Date: 02/22/2007
• Status: Expired due to Fees

• Current Assignee: Conversant Intellectual Property Management Inc (MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management))
• Original Assignee: MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management)
• Inventors: Kim, Jin-Ki, Oh, HakJune, Pyeon, Hong Beom
• Primary Examiner(s): Kim; Matt
• Assistant Examiner(s): Dudek, Jr.; Edward J
• Application Number:
  US12/832,121
• Publication Number:
  US 20100275056A1
• Time in Patent Office: 250 Days
• Field of Search: 711/103, 711/118, 711/154, 711/E12.008, 710/52
• US Class Current: 711/103
• CPC Class Codes: G06F 13/4243 with synchronous protocol
• CPC Class Codes: G06F 13/4247 on a daisy chain bus

Abstract

An apparatus and method of page program operation is provided. When performing a page program operation with a selected memory device, a memory controller loads the data into the page buffer of one selected memory device and also into the page buffer of another selected memory device in order to store a back-up copy of the data. In the event that the data is not successfully programmed into the memory cells of the one selected memory device, then the memory controller recovers the data from the page buffer of the other memory device. Since a copy of the data is stored in the page buffer of the other memory device, the memory controller does not need to locally store the data in its data storage elements.

Claims

1. A system comprising:

a plurality of memory devices that are interconnected in-series, each memory device having a page buffer and memory cells, each of the plurality of memory devices having a unique device address; and

an apparatus for controlling the plurality of memory devices, the apparatus comprising a data processor configured

to execute a page program operation with a mirror back-up of data by;

providing a device address for selecting one of the plurality of memory devices as a selected memory device, the provided device address being compared to the unique device address to identify the selected memory device;

writing data to the page buffer of the selected memory device of the plurality of memory devices and to the page buffer of another memory device of the plurality of memory devices;

instructing the selected memory device to program the data loaded in its page buffer into its memory cells; and

determining whether the data is not successfully programmed into the memory cells of the selected memory device, recover the data from the page buffer of the another memory device,

to recover the data from the page buffer of the another memory device by;

reading back the data from the page buffer of the another memory device without programming the data into the memory cells of the another memory device,

to transmit a single command for writing the data to both the page buffer of the selected memory device and the page buffer of the another memory device,

to write the data to both the page buffer of the selected memory device and the page buffer of the another memory device by;

broadcasting a first message to inform all of the memory devices to enter a multi-address detection mode in which the another memory device will process commands addressed to the selected memory device;

sending the single command for writing the data to both the page buffer of the selected memory device and the page buffer of the another memory device; and

broadcasting a second message to inform all of the memory devices to exit the multi-address detection mode.

2. The system of claim 1, wherein the apparatus further comprises:

data storage for storing the data prior to writing the data to the page buffer of the selected memory device and to the page buffer of the another memory device,

the apparatus being further configured to free up space in the data storage where the data is occupied before determining whether the data has been successfully programmed into the memory cells of the selected memory device.

3. The system of claim 1, wherein the apparatus further comprises:

an output connection connected to a first memory device of the plurality of memory devices; and

an input connection connected to a last memory device of the plurality of memory devices.

4. The system of claim 1, wherein the data processor of the apparatus is configured to execute another operation before determining whether the data has been successfully programmed into the memory cells of the selected memory device.

5. The system of claim 1 wherein the data processor of the apparatus is configured to execute at least one of:

upon recovering the data, re-attempt to program the data into the memory cells of the selected memory device but at a different address;

upon recovering the data, attempt to program the data into the memory cells of another selected memory device; and

upon recovering the data, store the data back in the data storage.

6. A method for controlling a plurality of memory devices that are interconnected in-series, each memory device having a page buffer and memory cells, each of the plurality of memory devices having a unique device address, the method comprising:

providing a device address for selecting one of the plurality of memory devices as a selected memory device;

identifying the selected memory device in comparison of the provided device address to the unique device address;

writing data to the page buffer of the selected memory device of the plurality of memory devices and to the page buffer of another memory device of the plurality of memory devices;

instructing the selected memory device to program the data loaded in its page buffer into its memory cells;

determining whether the data is not successfully programmed into the memory cells of the selected memory device, recover the data from the page buffer of the another memory device,

reading back the data from the page buffer of the another memory device without programming the data into the memory cells of the another memory device,

writing the data to both the page buffer of the selected memory device and the page buffer of the another memory device,

broadcasting a first message to inform all of the memory devices to enter a multi-address detection mode in which the another memory device will process commands addressed to the selected memory device;

sending the single command for writing the data to both the page buffer of the selected memory device and the page buffer of the another memory device; and

broadcasting a second message to inform all of the memory devices to exit the multi-address detection mode.

7. The method of claim 6 further comprising:

storing the data prior to writing the data to the page buffer of the selected memory device and to the page buffer of the another memory device;

freeing up space where the data is occupied before determining whether the data has been successfully programmed into the memory cells of the selected memory device.