Method and system for controlling memory accesses to memory modules having a memory hub architecture

• US 7,908,452 B2
• Filed: 04/05/2010
• Issued: 03/15/2011
• Est. Priority Date: 08/29/2002
• Status: Expired due to Fees

• Current Assignee: Round Rock Research LLC
• Original Assignee: Round Rock Research LLC
• Inventors: Jeddeloh, Joseph M., Lee, Terry R.
• Primary Examiner(s): Peugh; Brian R
• Application Number:
  US12/754,011
• Publication Number:
  US 20100191924A1
• Time in Patent Office: 344 Days
• Field of Search: None
• US Class Current: 711/169
• CPC Class Codes: G06F 13/1642 with request queuing
• CPC Class Codes: G06F 13/1673 using buffers

Abstract

A computer system includes a memory hub controller coupled to a plurality of memory modules. The memory hub controller includes a memory request queue that couples memory requests and corresponding request identifier to the memory modules. Each of the memory modules accesses memory devices based on the memory requests and generates response status signals from the request identifier when the corresponding memory request is serviced. These response status signals are coupled from the memory modules to the memory hub controller along with or separate from any read data. The memory hub controller uses the response status signal to control the coupling of memory requests to the memory modules and thereby control the number of outstanding memory requests in each of the memory modules.

Claims

1. A system comprising:

at least one memory device operable to output read data signals; and

a response generator coupled to the at least one memory device, the response generator having a first input terminal operable to receive the read data signals from the at least one memory device, a second input terminal operable to receive read status signals, the read status signals identifying read requests corresponding to each read data signal, and an output terminal, the response generator operable to generate read responses each comprising one of the read data signals and corresponding read status signals, the response generator further being operable to transmit the read responses from the output terminal.

2. The device of claim 1 wherein the first input terminal is coupled to a flow control unit and the second input terminal is coupled to a read queue.

3. The device of claim 1 further comprising a third input terminal operable to receive write signals, the second input terminal further operable to receive write status signals, the generator further being operable to generate write responses each comprising the write status signal.